The invention concerns a method of manufacturing an assembly of electronic components (3) on the front surface of a semiconductor wafer (1) comprising a plurality of field areas (4), each area (4) comprising at least one field (2) and each field (2) comprising at least one electronic component (3). The method comprises a plurality of photolithography steps to form a stack of layers forming each electronic component (3), each photolithography step comprises the application of a mask successively on each field (2) in photolithography equipment. One of the masks further comprises an identification pattern, said mask being called identification mask. At the photolithography step associated with the identification mask, as least one photolithographic parameter of the photolithography equipment is different for each field area (4), to expose the identification pattern differently in each field area (4).

A semiconductor structure includes a functional die, a dummy die, a conductive feature, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The conductive feature is electrically connected to the functional die. The seal ring is disposed aside the conductive feature. The alignment mark is disposed between the seal ring and the conductive feature, and the alignment mark is electrically isolated from the dummy die, the conductive feature and the seal ring.

A method for aligning to a pattern on a wafer is disclosed. The method includes the steps of obtaining a first inline image from a first sample wafer, obtaining a first contour pattern of an alignment mark pattern from the first inline image, using the first contour pattern to generate a first synthetic image in black and white pixels of only two grayscale levels, using the first synthetic image as a reference to recognize the alignment mark pattern on a tested wafer, and aligning to a tested pattern on the tested wafer according to a position of the alignment mark pattern on the tested wafer and a coordinate information.

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including alignment marks; measuring a position of the wafer by measuring positions of the alignment marks with one or more cameras; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.

A printed circuit board includes a substrate base; a plurality of ball lands arranged on a surface of the substrate base; a cutting position identification mark disposed on a corner of the surface of the substrate base; and at least one alignment mark disposed on the surface of the substrate base to be spaced apart from the ball lands and exposed to the outside, wherein top surfaces of the ball lands and a top surface of the at least one alignment mark are at substantially the same vertical level and the ball lands and the at least one alignment mark include the same material.

A method for fabricating an integrated circuit structure is provided. The method includes forming an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack comprises a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately arranged over the semiconductor substrate; patterning the epitaxial stack into a first fin and a second fin, wherein from a top view the first fin extends along a first direction, and the second fin has a first fin line extending along the first direction and a second fin line extending along a second direction different from the first direction; forming a first gate structure over a first portion of the first fin; etching a recess in a second portion of the first fin adjacent the first portion of the first fin; and forming a source/drain feature in the recess.

A semiconductor package including a lower substrate, a lower semiconductor chip mounted on the lower substrate, a lower mold layer on the lower substrate and enclosing the lower semiconductor chip, a redistribution layer on the lower mold layer, and a vertical connection terminal around the lower semiconductor chip and connecting the lower substrate to the redistribution layer may be provided. The lower semiconductor chip may include a cognition mark at a top surface thereof. The cognition mark may include a marking pattern having an intaglio shape at the top surface of the lower semiconductor chip, and a molding pattern filling an inner space of the marking pattern. A first material constituting the molding pattern may be the same as a second material constituting the lower mold layer.

A semiconductor package and a method of forming the same are provided. The semiconductor package includes a semiconductor die and a redistribution structure disposed on the semiconductor die. The redistribution structure includes an alignment auxiliary layer, a plurality of dielectric layers and a plurality of conductive patterns. The alignment auxiliary layer has a light transmittance for a light with a wavelength range of about 350-550 nm lower than that of one of the plurality of dielectric layers.

Methods of fabricating a 3D semiconductor device including: forming a first level including a first single crystal layer and first transistors, includes a single crystal channel; forming a first metal layer in the first level and a second metal layer overlaying the first metal layer; forming memory control circuits in the first level; forming a second level including second transistors, where at least one of the second transistors includes a metal gate; forming a third level including third transistors; forming a fourth level including fourth transistors, where the second level includes first memory cells, where the fourth level includes second memory cells, where the memory control circuits include control of data written into the first memory cells and into the second memory cells, where at least one of the transistors includes a hafnium oxide gate dielectric.