The invention concerns a method of manufacturing an assembly of electronic components (3) on the front surface of a semiconductor wafer (1) comprising a plurality of field areas (4), each area (4) comprising at least one field (2) and each field (2) comprising at least one electronic component (3). The method comprises a plurality of photolithography steps to form a stack of layers forming each electronic component (3), each photolithography step comprises the application of a mask successively on each field (2) in photolithography equipment. One of the masks further comprises an identification pattern, said mask being called identification mask. At the photolithography step associated with the identification mask, as least one photolithographic parameter of the photolithography equipment is different for each field area (4), to expose the identification pattern differently in each field area (4).

A substrate includes: a first die alignment mark and a first die position mark defining a die stack region. The first die alignment mark has substantially a cross shape having substantially a vertical bar and substantially a horizontal bar intersecting each other substantially perpendicularly, and the first die position mark includes a first main position mark having a first area and a first branch position mark having a second area different from the first area.

An embodiment semiconductor device includes an interposer, a semiconductor die electrically connected to the interposer, an integrated passive device die electrically connected to the interposer, the integrated passive device die including two or more seal rings, and a first alignment mark formed on the integrated passive device die within a first area enclosed by a first one of the two or more seal rings. The integrated passive device die may further include two or more integrated passive devices located within respective areas enclosed by respective ones of the two or more seal rings. Each of the two or more integrated passive devices may include electrical connections that are formed as a plurality of micro-bumps, and the first alignment mark may be electrically isolated from the electrical connections, and the first alignment mark and the electrical connections may share a common material.

A semiconductor package may include: a first double-chip structure including a first semiconductor chip, a second semiconductor chip, a first scribe lane region dividing the first semiconductor chip and the second semiconductor chip, and a first through hole in the first scribe lane region; a second double-chip structure on the first double-chip structure, the second double-chip structure including a third semiconductor chip, a fourth semiconductor chip, a second scribe lane region dividing the third semiconductor chip and the fourth semiconductor chip, and a second through hole in the second scribe lane region; first conductive connection members between the first and second double-chip structures and configured to electrically connect the first and third semiconductor chips and the second and fourth semiconductor chips; and a molding member on the first double-chip structure and the second double-chip structure and in the first through hole and the second through hole.