Provided are a semiconductor structure and a method of forming the same. The semiconductor structure includes: a substrate, an under bump metallurgy (UBM) structure, and a solder. The UBM structure is disposed over the substrate. The UBM structure includes a first metal layer; a second metal layer disposed on the first metal layer; and a third metal layer disposed on the second metal layer. A sidewall of the first metal layer is substantially aligned with a sidewall of the second metal layer, and a sidewall of the third metal layer is laterally offset inwardly from the sidewalls of the first and second metal layers. The solder is disposed on the third metal layer.

A method of electroplating a metal into features, having substantially different depths, of a partially fabricated electronic device on a substrate is provided. The method includes adsorbing accelerator into the bottom of recessed features; partially filling the features by a bottom up fill mechanism in an electroplating solution; diffusing leveler into shallow features to decrease the plating rate in shallow features as compared to deep features; and electroplating more metal into the features such that the height of metal in deep features is similar to the height of metal in shallow features.

A semiconductor package including: a semiconductor package comprising a first semiconductor chip which includes a first face and a second face opposite to each other in a first direction, a first insulating layer which is disposed on the first face, and includes vias connected to each connecting pad of the first semiconductor chip, redistribution patterns which are disposed on the first insulating layer, under bump metal layers (UBM) which are respectively disposed on the redistribution patterns, a second insulating layer which covers a part of each of the redistribution patterns, and solder bumps which are respectively disposed on the UBMs, wherein the first insulating layer includes a third face and a fourth face opposite to the third face in the first direction, wherein the third face is adjacent to the first face, and a part of the fourth face does not overlap the second insulating layer in the first direction.

In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump.

In some examples, a method for manufacturing a semiconductor package comprises forming a copper member on a surface; applying a photoresist to the copper member and the surface; and forming a cavity in the photoresist above the copper member. The cavity has a first volume with a first diameter and a second volume with a second diameter larger than the first diameter. The second volume is more proximal to the copper member than the first volume. The method also includes forming a nickel member in the second volume forming a palladium member in the first volume.

Disclosed is a method for preparing a display substrate, including: providing a driving substrate; wherein the driving substrate includes: a base substrate; a pixel driving circuit layer; a first pad and a second pad, spaced from each other, and connected to the pixel driving circuit layer; and an electrostatic protection alignment, spaced from the first pad; and transferring a light-emitting element to the driving substrate, such that an anode of the light-emitting element is connected in alignment with the first pad and a cathode of the light emitting-element is connected in alignment with the second pad. The first pad includes a first toothed tip arranged on a side of the first pad facing the electrostatic protection alignment, and the electrostatic protection alignment includes a second toothed tip arranged on a side of the electrostatic protection alignment facing the first pad.

A contact structure and a method of forming the contact structure. The contact structure includes: a metallic contact; a flexible dielectric material; and an interlevel dielectric material surrounding, and in direct contact with, both the metallic contact and the flexible dielectric material. The flexible dielectric material has a lower modulus of elasticity than does the interlevel dielectric material. The flexible dielectric material and the interlevel dielectric material are different dielectric materials. The flexible dielectric material may be positioned to be compressed in response to a shearing force generated at an interface between the flexible dielectric material and the metallic contact during expansion of the metallic contact. The metallic contact may include a bottom portion and a top portion, wherein the top portion includes an upper part and a lower part, and wherein the flexible dielectric material is in direct contact with the lower part of the top portion.

A semiconductor device and method of fabrication are described. The device includes a semiconductor RFID IC base layer; a passivation layer located over the base layer and including a metal insert within the passivation layer; a repassivation layer located over the passivation layer and the metal insert; an assembly pad layer located over the repassivation layer. The device includes a first region R1 of the device, where a height of the repassivation layer is given by d.sub.1, and a region R1 is provided with an assembly pad in the assembly pad layer over the repassivation layer that has an area A.sub.1. The device includes an nth region RN of the device, where the height of the repassivation layer is given by d.sub.n, where d.sub.1>d.sub.n, and the region RN is provided with an assembly pad in the bump layer over the repassivation layer, which has an area A.sub.n, where A.sub.n>A.sub.1.