Provided are a semiconductor structure and a method of forming the same. The semiconductor structure includes: a substrate, an under bump metallurgy (UBM) structure, and a solder. The UBM structure is disposed over the substrate. The UBM structure includes a first metal layer; a second metal layer disposed on the first metal layer; and a third metal layer disposed on the second metal layer. A sidewall of the first metal layer is substantially aligned with a sidewall of the second metal layer, and a sidewall of the third metal layer is laterally offset inwardly from the sidewalls of the first and second metal layers. The solder is disposed on the third metal layer.

Embodiments of the present disclosure relate to a method of digital lithography for semiconductor packaging and a software application. The method includes receiving metrology data to a digital lithography system, the metrology data corresponding to the pillar heights and pillar critical dimensions of a plurality of non-uniform pillars disposed over the die, wherein at least two pillars have different pillar heights and different pillar critical dimensions, the digital lithography system is operable to update a mask pattern, the mask pattern corresponding to a pattern of uniform pillars, updating the mask pattern according to the metrology data to generate a compensated mask pattern, and conducting a digital lithography process to pattern on a resist to form a plurality of vias, the vias are formed over each non-uniform pillar of the plurality of non-uniform pillars and include a via depth and a via critical dimension after the resist is developed.

A semiconductor package is provided. The semiconductor package includes a semiconductor device bonded to a base through a first conductive structure. The semiconductor device includes a carrier substrate including a conductive trace. A portion of the conductive trace is elongated. The semiconductor device also includes a second conductive structure above the carrier substrate. A portion of the second conductive structure is in contact with the portion of the conductive trace. The semiconductor device further includes a semiconductor body mounted above the conductive trace. The semiconductor body is connected to the second conductive structure.

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

A method of increasing a volume and a height of a solder bump present on a contact pad of a substrate is provided, including the steps: a) placing a solder ball having a predetermined volume in a capillary which is placed over the solder bump, b) liquefying the solder ball by applying laser energy from the laser source to the solder ball through the capillary, c) ejecting the liquefied solder ball from the capillary onto the solder bump by applying pressurized gas to the liquefied solder ball through the capillary, and d) melting the solder bump by transferring thermal and kinetic energy to the solder bump from the ejected liquefied solder ball and merging the liquefied solder ball with the melted solder bump.

A described example includes: a passive component die mounted to a device side surface of a semiconductor device die, and extending away from the device side surface of the semiconductor device die; the semiconductor device die and the passive component die flip chip mounted to a device mounting surface of a package substrate including a cavity extending into the package substrate from the device mounting surface of the package substrate, the cavity in a position corresponding to the passive component die, the passive component die extending into the cavity of the package substrate, and the package substrate having terminals on a board side surface; and mold compound covering the semiconductor device die, the passive component die, and the device mounting surface of the package substrate, the mold compound forming the body of a microelectronic device package, the terminals of the package substrate forming terminals of the microelectronic device package.

A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.

Semiconductor devices including the use of solder materials and methods of manufacturing are provided. In embodiments the solder materials utilize a first tensile raising material, a second tensile raising material, and a eutectic modifier material. By utilizing the materials a solder material can be formed and used with a reduced presence of needles that may otherwise form during the placement and use of the solder material.

A semiconductor device has a semiconductor substrate and first insulating layer formed over the surface of the semiconductor substrate. A dummy via is formed through the first insulating layer. A second insulating layer is formed over the first insulating layer to fill the dummy via. A first conductive layer is formed over the second insulating layer. A bump is formed over the first conductive layer adjacent to the dummy via filled with the second insulating layer. A second conductive layer is formed over a surface of the semiconductor substrate. The dummy via filled with the second insulating layer relieves stress on the second conductive layer. A plurality of dummy vias filled with the second insulating layer can be formed within a designated via formation area. A plurality of dummy vias filled with the second insulating layer can be formed in a pattern.

A method includes: providing a support substrate covered by a separation layer, a seed layer, a resin layer having openings; forming, through the openings, interconnection elements by depositing a solder layer, a copper pillar, and optionally a gold layer; removing the resin, and etching the non-covered portion of the seed layer; assembling the interconnection elements to an assembly comprising a substrate in which are formed first chips and second chips assembled to the first chips; wherein the interconnection elements are assembled by thermocompression onto conductive landing areas positioned on the substrate coupled to the first chips; and removing the temporary support and the separation layer.