Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first substrate having first pads on a first surface of the first substrate, a second substrate on the first substrate and having a plurality of second pads on a second surface of the second substrate, and connection terminals between the first substrate and the second substrate and correspondingly coupling the first pad to the second pads. Each of the connection terminals has a first major axis and a first minor axis that are parallel to the first surface of the first substrate and are orthogonal to each other. When viewed in a plan view, the first minor axis of each of the connection terminals is directed toward a center of the first substrate.

A method includes providing an interposer structure including conductive paths, forming micro bumps over the interposer structure and connected to the conductive paths, bonding a first die and a second die onto the micro bumps, forming a molding compound over and around the first die and the second die, performing a planarization process to expose a top surface of the second die, forming a trench in the molding compound to expose a top surface of the first die, forming a thermal interface material (TIM) layer in the trench and over the top surface of the second die, bonding the interposer structure to a substrate, and attaching a heat sink onto the TIM layer. The first die has a first height and the second die has a second height greater than the first height.

An integrated device comprising a die substrate; a die interconnection portion coupled to the die substrate; and a metallization interconnect coupled to the die interconnection portion. The metallization interconnect comprises an adhesion metal layer, a first metal layer coupled to the adhesion metal layer; a second metal layer coupled to the first metal layer, and a third metal layer coupled to the second metal layer.

An IC package includes one or more microelectronic devices, a plurality of package bumps disposed at a first side, and a metal structure electrically connecting at least a first device contact pad of a first microelectronic device and at least a first package bump of the plurality of package bumps. The metal structure includes an RDL trace extending between a first region aligned with the first device contact pad and a second region aligned with the first package bump, wherein the first package bump is mechanically and electrically connected directly to the second region of the RDL trace. The metal structure further includes a first via extending between the first region of the RDL trace and the first device contact pad and further includes a set of one or more support studs extending from the second region to a support surface facing the first side.

A semiconductor device capable of suppressing a bonding defect between a bump of a semiconductor chip and a land of a wiring substrate is provided. The semiconductor device includes the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a wiring layer, a protective film, a first bump and a second bump. The wiring layer is formed on the semiconductor substrate and has a first bonding pad and a second bonding pad. The first bonding pad has a first upper surface. The second bonding pad has a second upper surface. The protective film is formed on the wiring layer so as to cover the first bonding pad and the second bonding pad. The protective film has a first opening portion overlapping the first bonding pad and penetrating through the protective film, and a second opening portion overlapping the second bonding pad and penetrating through the protective film.

In some embodiments, a device includes a chip-on-interposer structure on a first side of a package substrate, and a first ring structure on the first side of the package substrate. The first ring structure extends around a perimeter of the chip-on-interposer structure. A lid may be disposed on the first ring structure. The device may also include an array of connectors on a second side of the package substrate, wherein the second side of the package substrate is opposite a first side of the package substrate. A second ring structure may be on the second side of the package substrate. The second ring structure is positioned around a perimeter of the array of connectors.

The present disclosure relates to a method of bonding column type deposits to a substrate, and more specifically, to a method of bonding to a substrate column type deposits, which are formed in a column shape and connect the substrate and electrodes of a semiconductor chip so as to connect the semiconductor chip to the substrate. A method of bonding column type deposits to a substrate according to the present disclosure has the advantage of bonding the column type deposits having a high aspect ratio to accurate positions while being aligned vertically on the substrate.

An electronic device having a substrate employing reduced area, added metal pad(s) to a metal interconnect(s) to reduce air voids in a solder joint and related fabrication methods are disclosed. The electronic device includes a die that has die interconnects coupled to a first metal pad(s) of a respective metal interconnect(s) of a metallization layer of the substrate through a second, additional metal pad(s). To facilitate a reduction in air voids in the solder joint between the die and the first metal pad(s) and consequently the amount of solder between the first metal pad and the die, the second, additional metal pad(s) having a reduced cross-sectional area from the first metal pad(s) is above and adjacent to the first metal pad(s). A solder joint(s) is employed to couple the second, additional metal pad(s) to a die interconnect(s) of the die to couple the die to the substrate.

A circuit package includes a photonic integrated circuit (PIC) and four electronic integrated circuits (EIC) electrically connected to and physically overlapping a first surface of the PIC. An optical interface for coupling optical signals into and/or out of the PIC is coupled to a substrate that is attached to a second surface of the PIC opposite the first surface of the PIC. Each EIC includes an analog-mixed signal (AMS) block located at or near a geometric center of the respective EIC. The PIC includes four active regions located at respective corners of the PIC. Each active region of the PIC is coupled to the respective AMS block.

A semiconductor package and a method for manufacturing a semiconductor package includes a base substrate including a first surface and a second surface, a first contact pad disposed on the first surface of the base substrate, a first solder resist layer disposed on the first surface of the base substrate, a second solder resist layer covering a portion of an upper surface of the first solder resist layer, and a first connector disposed in the first opening area and the second opening area. The first solder resist layer covers a side surface and a portion of an upper surface of the first contact pad, and defines a first opening area on the first contact pad. The first connector is in contact with the first contact pad. A first width of the first opening area is smaller than a second width of the second opening area.