Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; a lid surrounding an individual die, wherein the lid includes a planar portion and two or more sides extending from the planar portion, and wherein the individual die is electrically coupled to the substrate by interconnects; and a material surrounding the interconnects and coupling the two or more sides of the lid to the substrate.

A ring structure on a package substrate is divided into at least four different components, including a plurality of first pieces and a plurality of second pieces. By dividing the ring structure into at least four different components, the ring structure reduces flexibility of the package substrate, which thus reduces stress on a molding compound (e.g., in a range from approximately 1% to approximately 10%). As a result, molding cracking is reduced, which reduces defect rates and increases yield. Accordingly, raw materials, power, and processing resources are conserved that would otherwise be consumed with manufacturing additional packages when defect rates are higher.

An electronic device package includes a frame, an electronic device mounted to the frame, surface-mount leads, and a gel at least partially filling a cavity between the electronic device and the frame. The electronic device includes electronic circuitry provided on an electronic device substrate, and the surface-mount leads are electrically connected to the electronic circuitry and extend laterally and outwardly from an outer perimeter of the frame. The gel in the cavity covers the electronic circuitry.

In examples, a semiconductor package includes a substrate including a first opening; a first semiconductor die coupled to the substrate and including a microelectromechanical systems (MEMS) membrane, the first semiconductor die including a scalloped outer surface having multiple concavities; a second semiconductor die coupled to the substrate and configured to control the first semiconductor die; bond wires coupling the first and second semiconductor dies to the substrate; and a protective enclosure covering the substrate, the first and second semiconductor dies, and the bond wires.