A self-densifying interconnection is formed between a high-temperature semiconductor device selected from a GaN or SiC-based device and a substrate. The interconnection includes a matrix of micron-sized silver particles in an amount from approximately 10 to 60 weight percent; the micron-sized silver particles having a particle size ranging from approximately 0.1 microns to 15 microns. Bonding particles are used to chemically bind the matrix of micron-sized silver particles. The bonding particles are core silver nanoparticles with in-situ formed surface silver nanoparticles chemically bound to the surface of the core silver nanoparticles and, at the same time, chemically bound to the matrix of micron-sized silver particles. The bonding particles have a core particle size ranging from approximately 10 to approximately 100 nanometers while the in-situ formed surface silver nanoparticles have a particle size of approximately 3-9 nanometers.

The disclosure relates to assemblies and methods for preheating objects in the process of underfill. Specifically, the disclosure relates to assemblies and methods for treating printed circuit boards (PCBs), integrated circuits (ICs) wafers and the like, in the preheating stage of the underfill process using an assembly operable to create a customizable hot-air bath with adjustable depth to account for surface topology and necessary clearances, for soaking the PCBs, ICs, wafers and the like in hot air, bringing these to operating temperature.

A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate, the first bonding layer including a first bonding sub-layer and a second bonding sub-layer, the first bonding sub-layer including a first metal oxide material in an amorphous state and a plurality of metal nanoparticles, the second bonding sub-layer including a second metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, the second bonding layer including a third metal oxide material in an amorphous state; conducting a surface modification process on the first and second bonding layers; bonding the device and carrier substrates to each other through the first and second bonding layers; and annealing the first and second bonding layers to convert the first, second, and third metal oxide materials from the amorphous state to a crystalline state.

A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate formed with a semiconductor device so as to cover the semiconductor device, wherein the first bonding layer includes a first metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, wherein the second bonding layer includes a second metal oxide material in an amorphous state; conducting a surface modification process on the first bonding layer and the second bonding layer; bonding the device substrate and the carrier substrate to each other through the first and second bonding layers; and annealing the first and second bonding layers so as to convert the first and second metal oxide materials from the amorphous state to a crystalline state.

There are provided a thermosetting resin composition for semiconductor bonding and a thermosetting resin composition for light emitting device which have high thermal conductivity and an excellent heat dissipation property and are capable of reliable pressure-free bonding of a semiconductor element and a light emitting element to a substrate. A thermosetting resin composition comprising: (A) silver fine particles ranging from 1 nm to 200 nm in thickness or in minor axis; (B) a silver powder having an average particle size of more than 0.2 m and 30 m or less; (C) resin particles; and (D) a thermosetting resin, wherein an amount of the resin particles (C) is 0.01 to 1 part by mass and an amount of the thermosetting resin (D) is 1 to 20 parts by mass, to 100 parts by mass being a total amount of the silver fine particles (A) and the silver powder (B).

An electronic device having a substrate employing reduced area, added metal pad(s) to a metal interconnect(s) to reduce air voids in a solder joint and related fabrication methods are disclosed. The electronic device includes a die that has die interconnects coupled to a first metal pad(s) of a respective metal interconnect(s) of a metallization layer of the substrate through a second, additional metal pad(s). To facilitate a reduction in air voids in the solder joint between the die and the first metal pad(s) and consequently the amount of solder between the first metal pad and the die, the second, additional metal pad(s) having a reduced cross-sectional area from the first metal pad(s) is above and adjacent to the first metal pad(s). A solder joint(s) is employed to couple the second, additional metal pad(s) to a die interconnect(s) of the die to couple the die to the substrate.

A device includes: a first substrate; a second substrate; interconnects bonding the first substrate to the second substrate; and a polymer brush-based underfill layer in a gap between the first substrate and the second substrate. A method includes: attaching initiator molecules to one or more surfaces in a gap between a first substrate and a second substrate of a bonded structure, where the first substrate and the second substrate are bonded by interconnects; growing polymer chains from the initiator molecules; and annealing the bonded structure to form an underfill layer from the polymer chains in the gap.