Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a substrate, a first integrated circuit die over the substrate including a first recess that penetrates into a first edge of the first integrated circuit die, and a second integrated circuit die over the first integrated circuit die including a second recess that penetrates into a second edge of the second integrated circuit die. The semiconductor device assembly includes a pillar structure that uses the first recess and the second recess to align perimeters of the first integrated circuit die and the second integrated circuit die.

A method of forming a semiconductor package includes forming, on a first semiconductor chip, a plurality of inner connection terminals and a preliminary underfill covering the plurality of inner connection terminals, stacking the first semiconductor chip on a lower structure such that the preliminary underfill is bonded between the first semiconductor chip and the lower structure, and curing the preliminary underfill using a laser bonding process, thereby forming a first underfill, and reflowing the plurality of inner connection terminals during a formation of the first underfill through the curing of the preliminary underfill.

A semiconductor device includes a dielectric interposer, a first RDL, a second RDL, and a plurality of conductive structures. The dielectric interposer has a first surface and a second surface opposite to the first surface. The first RDL is disposed over the first surface of the dielectric interposer. The second RDL is disposed over the second surface of the dielectric interposer. The conductive structures are disposed through the dielectric interposer and directly contact the dielectric interposer. The conductive structures are electrically connected to the first RDL and the second RDL. Each of the conductive structures has a tapered profile. A minimum width of each of the conductive structures is proximal to the first RDL, and a maximum width of each of the conductive structures is proximal to the second RDL.

A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.

The present disclosure relates to an electronic device comprising a wafer comprising a first upper surface having at least one first contact arranged thereon; and at least one die comprising a second upper surface having at least one second contact arranged thereon, and at least one first lateral surface orthogonal to the second upper surface, said first contact being coupled to said second contact by a connector comprising one first conductive pillar formed on said first contact of said wafer; one second conductive pillar formed on said second contact of said die; and at least one conductive ball positioned in contact with at least a first upper portion of said first pillar(s) and in contact with at least one second upper portion of said second pillar(s).

A semiconductor device has a substrate. The substrate is disposed on a quartz carrier. An electrical component is disposed over the substrate opposite the quartz carrier. An epoxy-solder paste bump is disposed between the substrate and electrical component. The epoxy-solder paste bump comprises an epoxy and a solder powder disposed in the epoxy. Laser energy is applied to a surface of the substrate through the quartz carrier. The laser energy is converted to thermal energy to reflow the solder powder and cure the epoxy.

In a bonding process of a flip chip bonding method, a chip is bonded to contact pads of a substrate by composite bumps which each includes a raiser, a UBM layer and a bonding layer. Before the bonding process, the surface of the bonding layer facing toward the substrate is referred to as a surface to be bonded. During the bonding process, the surface to be bonded is boned to the contact pad and become a bonding surface on the contact pad. The bonding surface has an area greater than that of the surface to be bonded so as to reduce electrical impedance between the chip and the substrate.

A semiconductor package and a manufacturing method thereof are described. The semiconductor package includes a package having dies encapsulated by an encapsulant, a redistribution circuit structure, first and second modules and affixing blocks. The redistribution circuit structure is disposed on the package. The first and second modules are disposed on and respectively electrically connected to the redistribution circuit structure by first and second connectors disposed there-between. The first and second modules are adjacent to each other and disposed side by side on the redistribution circuit structure. The affixing blocks are disposed on the redistribution circuit structure and between the first and second modules and the redistribution circuit structure. The affixing blocks include first footing portions located below the first module, second footing portions located below the second module, and exposed portions exposed from the first and second modules. The affixing blocks join the first and second modules to the redistribution circuit structure.