A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface. An electronic device is integrated into the top surface of the semiconductor substrate. A conductive power rail is positioned intermediate the top surface and the bottom surface of the semiconductor substrate. The conductive power rail is configured to conduct power to the electronic device.

Embodiments described herein may be related to apparatuses, processes, and techniques related to patterning and metallization to produce metal features on a substrate that have pitches less than 26 nm. Other embodiments may be described and/or claimed.

Methods of fabricating a 3D semiconductor device including: forming a first level including a first single crystal layer and first transistors, includes a single crystal channel; forming a first metal layer in the first level and a second metal layer overlaying the first metal layer; forming memory control circuits in the first level; forming a second level including second transistors, where at least one of the second transistors includes a metal gate; forming a third level including third transistors; forming a fourth level including fourth transistors, where the second level includes first memory cells, where the fourth level includes second memory cells, where the memory control circuits include control of data written into the first memory cells and into the second memory cells, where at least one of the transistors includes a hafnium oxide gate dielectric.

Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.

A semiconductor chip includes a semiconductor substrate that includes a front side and a back side that are opposite to each other, a circuit structure disposed on the front side of the semiconductor substrate, a first through via that penetrates the semiconductor substrate in a vertical direction perpendicular to the front side of the semiconductor substrate and is electrically connected to the circuit structure, and a dummy via buried in the semiconductor substrate, wherein a lower end of the dummy via is spaced apart from the back side of the semiconductor substrate.

In a method for forming a semiconductor device, a substrate is provided; a word line is formed in the substrate by taking a first face of the substrate as an upper surface; a connecting layer electrically connected to one end of the word line is formed in part of the substrate and on the substrate; a first conducting layer is formed on the connecting layer; and a conducting plug is formed in the substrate by taking a second face of the substrate as an upper surface. The conducting plug is electrically connected to another end of the word line and electrically connected to the first conducting layer via the word line. The first face and the second face are two faces of the substrate opposite to each other in a thickness direction of the substrate.

A three-terminal 2T0C memory cell is formed based on a dual-gate transistor. A second transistor used as a read transistor is disposed as the dual-gate transistor. A first control electrode of the second transistor is configured to store written data during a write operation, and a second control electrode of the second transistor is configured to control a current path between a bit line and a read word line. During the write operation, a cut-off voltage may be loaded to the read word line connected to the second control electrode of the second transistor, to control the second transistor to be turned off, and the current path between the bit line and the read word line may be blocked during the write operation. In comparison with a four-terminal 2T0C memory cell, complexity and an area of SA routing are reduced, and storage density can be effectively improved.

A 3D semiconductor device including: a first level with first transistors, a single-crystal layer and at least one metal layer which includes interconnects between the first transistors forming first control circuits with a plurality of sense amplifiers; the first metal layer(s) overlaid by a second metal layer which is overlaid by a second level which includes first memory-cells which include second transistors with a metal-gate, overlaid by a third level which includes second memory cells which include third transistors which control the data written to second memory cells; a fourth metal layer overlaying a third metal layer which overlays the third level; where third transistor gate locations are aligned to second transistor gate locations within greater than 0.2 nm error, the first transistors or the second transistors comprise at least two FinFet transistors, and two of the FinFet transistors each have different threshold voltages.

An assembly for a power semiconductor device comprises a main body based on SiC and a plurality of vias based on an electrically conductive material. The main body comprises a first layer having a first thickness and a second layer having a second thickness, wherein the second thickness is smaller than the first thickness. The first layer and the second layer are formed from SiC. The first layer can have a higher n-doping concentration than the second layer. The vias extend along a vertical direction from a bottom side of the first layer partially into the first layer towards the second layer, wherein the vias do not extend into the second layer.

A semiconductor device and a method for fabricating it are disclosed. In the method, second and first substrates are bonded to obtain increased operating efficiency. Moreover, a heat dissipation unit, which includes a heat-dissipating semiconductor layer and a first heat-dissipating metal channel extending through the heat-dissipating semiconductor layer and dielectric layers on a surface thereof, is bonded to a surface of the first substrate to accelerate dissipation of heat generated during operation of the second and first substrates, imparting improved heat dissipation capacities to the semiconductor device.