A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.

The semiconductor structure includes: a substrate; a first insulating dielectric layer disposed on the substrate; a front layer structure disposed in the first insulating dielectric layer; a second insulating dielectric layer disposed on the first insulating dielectric layer; a third insulating dielectric layer disposed on the second insulating dielectric layer; a current layer structure disposed in the third insulating dielectric layer, including a plurality of first conductive wires spaced apart from each other; a first interconnection structure passing through the second insulating dielectric layer to connect a portion of the first conductive wires and the front layer structure; and a second interconnection structure passing through the first insulating dielectric layer and the second insulating dielectric layer to connect a portion of the first conductive wires, the first interconnection structure and the second interconnection structure being isolated from each other.

Reliability is improved in a semiconductor device in which an annular trench is formed around a through hole. A semiconductor device includes a semiconductor substrate, a through wiring, a back surface insulating film, and an annular trench. A wiring layer is formed on a front surface of the semiconductor substrate. The through hole penetrates the semiconductor substrate. The through wiring is formed along a side surface of the through hole. The back surface insulating film covers a back surface of the semiconductor substrate with respect to the front surface. The annular trench surrounds the periphery of the through hole when viewed from a direction perpendicular to the back surface, and a cavity closed by the back surface insulating film when viewed from the direction parallel to the back surface is formed inside.

A wafer-level chip structure, a multiple-chip stacked and interconnected structure and a fabricating method thereof, wherein the wafer-level chip structure includes: a through-silicon via, which penetrates a wafer; a first surface including an active region, a multi-layered redistribution layer and a bump; and a second surface including an insulation dielectric layer, and a frustum transition structure connected with the through-silicon via. In an embodiment of the present application, a frustum type impedance transition structure is introduced into a position between a TSV exposed area on a backside of a wafer and a UBM so as to implement an impedance matching between TSV and UBM, thereby alleviating the problem of signal distortion that is caused by an abrupt change of impedance.