A semiconductor device includes: a channel having layers of silicon separated from each other; a metal gate in contact with the layers of silicon; source/drain regions adjacent to the metal gate; a frontside power rail extending through the layers of silicon; a dielectric separating the frontside power rail from the metal gate; a via-connect buried power rail extending through the dielectric and coupling the frontside power rail to the source/drain regions; and a backside power rail coupled to the frontside power rail. The layers of silicon are wrapped on three sides by the metal gate.

A microelectronic structure including a nanosheet transistor that includes a source/drain. A frontside contact that includes a first section located on the frontside of the source/drain and a via section that extends to the backside of the nanosheet transistor. A shallow isolation layer located around a portion of the via section the first frontside contact. A backside metal line located on a backside surface of the via section and located on a backside surface of the shallow trench isolation layer. A dielectric liner located along a sidewall of the backside metal line and located along a bottom surface of the backside metal line.

A semiconductor structure includes a backside contact, and a source/drain region fully disposed within the backside contact.

A method of forming a semiconductor device is provided. The method includes forming an etch stop layer on a substrate having a first thickness, forming an epitaxial layer on the etch stop layer, and forming a wafer device on the epitaxial layer. The wafer device is bonded to a bonding wafer using hybrid bonding. The substrate is then ground to a second thickness less than the first thickness and planarized to a third thickness less than the second thickness. A mask layer is deposited on a bottom surface of the etch stop layer, and at least one via opening is formed in the mask layer. The etch stop layer is selectively removed, and the mask layer is removed to expose the substrate at the third thickness.

A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.

An electronic system includes a first device and a second device bonded to the first device. The first device includes: a semiconductor substrate with an opening; a stack having metal layers and conductive vias; and a conductive layer including aluminum having a first face in contact with the stack and a second face, opposite the first face, that is partially exposed through the opening. The metal layers and the conductive vias of the stack are made of a conductive material different from aluminum.

A back-side ground and power-distribution network is formed on a semiconductor wafer substrate by selectively etching first and second back-side partial-substrate rail (PSR) trench openings through a back-side surface of the wafer substrate, selectively forming a plurality of defined n-type conductive regions and defined p-type conductive regions in the wafer substrate at the bottoms of the first and second back-side PSR trench openings in position for electrical contact with n-well and p-well regions, and then forming first and second back-side PSR conductors in the first and second back-side PSR trench openings to be directly electrically connected over the plurality of defined n-type conductive regions and defined p-type conductive regions to the n-well and p-well regions in the wafer substrate.

A backside power and ground distribution network is formed on a wafer substrate layer by selectively etching backside PSV openings through a backside surface of the wafer substrate layer, forming n-type and p-type conductive regions in the wafer substrate layer at the bottoms of first and second backside PSV openings in position for electrical contact with an n-well and p-well regions, and then forming first and second backside PSV conductors in the first and second backside PSV openings to be directly electrically connected over the n-type and p-type conductive regions to the n-well and p-well regions in the wafer substrate layer.

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) in which cavities separate wires of an interconnect structure. For example, a conductive feature overlies a substrate, and an intermetal dielectric (IMD) layer overlies the conductive feature. A first wire and a second wire neighbor in the IMD layer and respectively have a first sidewall and a second sidewall that face each other while being separated from each other by the IMD layer. Further, the first wire overlies and borders the conductive feature. A first cavity and a second cavity further separate the first and second sidewalls from each other. The first cavity separates the first sidewall from the IMD layer, and the second cavity separates the second sidewall from the IMD layer. The cavities reduce parasitic capacitance between the first and second wires and hence resistance-capacitance (RC) delay that degrades IC performance.

A semiconductor device includes: a first via level forming a bottom jumper configured to provide an output; a first set of two or more first metallization tracks overlying the first via level; a second via level forming a first top jumper overlying the first set of two or more first metallization tracks; and a second metallization track overlying the second via level.