An IC structure includes a first transistor, a second transistor, a dielectric fin, a dielectric cap, a backside metal structure, and a source/drain contact. The first transistor includes a first channel region, a first gate structure, and first source/drain features disposed on opposite sides of the first gate structure. The second transistor includes a second channel region, a second gate structure, and second source/drain features disposed on opposite sides of the second gate structure. The dielectric fin is disposed between the first and second transistors. The dielectric cap interfaces a backside surface of the dielectric fin. The source/drain contact abuts the dielectric fin and is electrically coupled to a first one of the first source/drain features by way of a silicide layer and electrically coupled to the backside metal rail by way of physical contact established by the source/drain contact and the backside metal rail.

A semiconductor device is provided. The semiconductor device includes: a first substrate; an active pattern extending on the first substrate; a gate electrode extending on the active pattern; a source/drain region on the active pattern; a first interlayer insulating layer on the source/drain region; a sacrificial layer on the first substrate; a lower wiring layer on a lower surface of the sacrificial layer; a through via trench extending to the lower wiring layer by passing through the first interlayer insulating layer and the sacrificial layer in a vertical direction; a through via inside the through via trench and connected to the lower wiring layer; a recess inside the sacrificial layer and protruding from a sidewall of the through via trench in the second horizontal direction; and a through via insulating layer extending along the sidewall of the through via trench and into the recess.

An integrated circuit (IC) chip is provided. In one aspect, a semiconductor substrate includes active devices at its front surface and power delivery tracks on its back surface. The active devices are powered through mutually parallel buried power rails, with the power delivery tracks running transversely with respect to the power rails, and connected to the power rails by a plurality of Through Semiconductor Via connections, which run from the power rails to the back of the substrate. The TSVs are elongate slit-shaped TSVs aligned to the power rails and arranged in a staggered pattern, so that any one of the power delivery tracks is connected to a first row of mutually parallel TSVs, and any power delivery track directly adjacent to the power delivery track is connected to another row of TSVs which are staggered relative to the TSVs of the first row. A method of producing an IC chip includes producing the slit-shaped TSVs before the buried power rails.

Provided is a backside power distribution network (BSPDN) semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device including an active device that includes an epitaxial layer, a second semiconductor device provided on a second surface of the wafer opposite to the first surface, the second semiconductor device including a power rail configured to supply power, and a through-silicon via (TSV) protruding from the power rail and extending to a level of the epitaxial layer of the active device.

A microelectronic structure is disclosed. The microelectronic structure can include a bulk semiconductor portion that has a first surface and a second surface opposite the first surface. The microelectronic structure can include a via structure that extends at least partially through the bulk semiconductor portion along a direction non-parallel to the first surface. The microelectronic structure can include a first dielectric barrier layer that is disposed on the first surface of the bulk semiconductor portion and extends to the via structure. The microelectronic structure can include a second dielectric layer that is disposed on the first dielectric barrier layer and extends to the via structure.