An IC structure includes a first transistor, a second transistor, a dielectric fin, a dielectric cap, a backside metal structure, and a source/drain contact. The first transistor includes a first channel region, a first gate structure, and first source/drain features disposed on opposite sides of the first gate structure. The second transistor includes a second channel region, a second gate structure, and second source/drain features disposed on opposite sides of the second gate structure. The dielectric fin is disposed between the first and second transistors. The dielectric cap interfaces a backside surface of the dielectric fin. The source/drain contact abuts the dielectric fin and is electrically coupled to a first one of the first source/drain features by way of a silicide layer and electrically coupled to the backside metal rail by way of physical contact established by the source/drain contact and the backside metal rail.

An embodiment semiconductor device may include a semiconductor die; one or more redistribution layers formed on a surface of the semiconductor die and electrically coupled to the semiconductor die; and an active or passive electrical device electrically coupled to the one or more redistribution layers. The active or passive electrical device may include a silicon substrate and a through-silicon-via formed in the silicon substrate. The active or passive electrical device may be configured as an integrated passive device including a deep trench capacitor or as a local silicon interconnect. The semiconductor device may further include a molding material matrix formed on a surface of the one or more redistribution layers such that the molding material matrix partially or completely surrounds the active or passive electrical device.

A package structure includes a first dielectric layer disposed on a first patterned circuit layer, a first conductive via in the first dielectric layer and electrically connected to the first patterned circuit layer, a circuit layer on the first dielectric layer, a second dielectric layer on the first dielectric layer and covering the circuit layer, a second patterned circuit layer on the second dielectric layer and including conductive features, a chip on the conductive features, and a molding layer disposed on the second dielectric layer and encapsulating the chip. The circuit layer includes a plurality of portions separated from each other and including a first portion and a second portion. The number of pads corresponding to the first portion is different from that of pads corresponding to the second portion. An orthographic projection of each portion overlaps orthographic projections of at least two of the conductive features.

A method of manufacturing a semiconductor package includes: forming through-vias extending from a front side of a semiconductor substrate into the substrate; forming, on the front side of the semiconductor substrate, a circuit structure including a wiring structure electrically connected to the through-vias; removing a portion of the semiconductor substrate so that at least a portion of each of the through-vias protrudes to a rear side of the semiconductor substrate; forming a passivation layer covering the protruding portion of each of the through-vias; forming trenches recessed along a periphery of a corresponding one of the through-vias; removing a portion of the passivation layer so that one end of each of the through-vias is exposed to the upper surface of the passivation layer; and forming backside pads including a dam structure in each of the trenches, the dam structure being spaced apart from the corresponding one of the through-vias.

A semiconductor device is provided. The semiconductor device includes: a first substrate; an active pattern extending on the first substrate; a gate electrode extending on the active pattern; a source/drain region on the active pattern; a first interlayer insulating layer on the source/drain region; a sacrificial layer on the first substrate; a lower wiring layer on a lower surface of the sacrificial layer; a through via trench extending to the lower wiring layer by passing through the first interlayer insulating layer and the sacrificial layer in a vertical direction; a through via inside the through via trench and connected to the lower wiring layer; a recess inside the sacrificial layer and protruding from a sidewall of the through via trench in the second horizontal direction; and a through via insulating layer extending along the sidewall of the through via trench and into the recess.

An integrated circuit (IC) chip is provided. In one aspect, a semiconductor substrate includes active devices at its front surface and power delivery tracks on its back surface. The active devices are powered through mutually parallel buried power rails, with the power delivery tracks running transversely with respect to the power rails, and connected to the power rails by a plurality of Through Semiconductor Via connections, which run from the power rails to the back of the substrate. The TSVs are elongate slit-shaped TSVs aligned to the power rails and arranged in a staggered pattern, so that any one of the power delivery tracks is connected to a first row of mutually parallel TSVs, and any power delivery track directly adjacent to the power delivery track is connected to another row of TSVs which are staggered relative to the TSVs of the first row. A method of producing an IC chip includes producing the slit-shaped TSVs before the buried power rails.

Provided is a backside power distribution network (BSPDN) semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device including an active device that includes an epitaxial layer, a second semiconductor device provided on a second surface of the wafer opposite to the first surface, the second semiconductor device including a power rail configured to supply power, and a through-silicon via (TSV) protruding from the power rail and extending to a level of the epitaxial layer of the active device.

Disclosed herein are methods for direct bonding. In some embodiments, the direct bonding method includes microwave annealing a dielectric bonding layer of a first element by exposing the dielectric bonding layer to microwave radiation and then directly bonding the dielectric bonding layer of the first element to a second element without an intervening adhesive. The bonding method also includes depositing the dielectric bonding layer on a semiconductor portion of the first element at a first temperature and microwave annealing the dielectric bonding layer at a second temperature lower than the first temperature.

Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first transistor device on a substrate, a second transistor device on the substrate, and a power rail between the first transistor device and the second transistor device. The power rail may include a first section with a first critical dimension (CD), a second section with a second CD, and a third section with a third CD.

A semiconductor structure includes a stacked device structure having a first field-effect transistor having a first source/drain region, and a second field-effect transistor vertically stacked above the first field-effect transistor, the second field-effect transistor having a second source/drain region and a gate region having first sidewall spacers. The stacked device structure further includes a frontside source/drain contact disposed on a first portion of a sidewall and a top surface of the second source/drain region, a first metal via connected to the frontside source/drain contact and to a first backside power line, and second sidewall spacers disposed on a first portion of the first metal via. The first sidewall spacers comprise a first dielectric material and the second sidewall spacers comprise a second dielectric material different than the first dielectric material.