A semiconductor device includes: a first lead including a base portion; a semiconductor element mounted on a first side of the base portion in the thickness direction and including a first electrode; a second lead spaced apart from the base portion in a first direction perpendicular to the thickness direction; a first conductive member electrically bonded to the first electrode and the second lead; and a sealing resin. The first conductive member includes a first portion bonded to the first electrode via a conductive first bonding layer. The first portion includes a first surface and a second surface respectively facing the first side and a second side in the thickness direction. The first portion includes a plurality of first recesses that are recessed from the first surface and a plurality of second recesses that are recessed from the second surface.

The purpose of this invention is to provide a semiconductor device that prevents defects in semiconductor elements caused by differences in thermal expansion and maintains low electrical resistance by directly or indirectly laminating an FeNi alloy metal layer onto the front-surface or back-surface electrodes of the semiconductor element. In this invention, an FeNi alloy metal layer is directly or indirectly applied on the surface electrodes of the semiconductor element, and the semiconductor element is connected to a conductor through the FeNi alloy metal layer. Depending on the application, the Ni content of the FeNi alloy metal layer is set within the range of 36% to 45% by weight, and the thickness of the FeNi alloy metal layer is set within the range of 2 m to 20 m.

A power module includes a first end power semiconductor element and a second end power semiconductor element. A first sum is a sum of a path length between the gate electrode of the first end power semiconductor element and a first control terminal and a path length between the source electrode of the first end power semiconductor element and a first detection terminal. A second sum is a sum of a path length between the gate electrode of the second end power semiconductor element and the first control terminal and a path length between the source electrode of the second end power semiconductor element and the first detection terminal. The power module includes a first control layer connected to the gate electrode. The first control layer includes a first detour portion that detours the path to reduce a difference between the first sum and the second sum.

A semiconductor device includes a first die pad having a main surface, a second die pad having a second main surface, a first switching element connected to the first main surface, a second switching element connected to the second main surface, a first connecting member connecting the first main surface electrode of the first switching element to the second die pad, an encapsulation resin encapsulating the first switching element, the second switching element, the first die pad, the second die pad, and the first connecting member, and leads projecting out of one of the resin side surfaces of the encapsulation resin.

A transistor device includes: a plurality of transistor cells in a semiconductor substrate; and a source pad above the semiconductor substrate and electrically connected to a source region and a body region of the transistor cells. A first group of the transistor cells has a first body region average doping concentration. A second group of the transistor cells has a second body region average doping concentration higher than the first body region average doping concentration. The transistor cells of the first and second groups are interleaved. The transistor cells have a first source region density in a first area of the semiconductor substrate underneath a region of the source pad designated for clip contacting, and a second source region density lower than the first source region density in a second area of the semiconductor substrate outside the first area.

A semiconductor die and an electrically conductive ribbon are arranged on a substrate. The electrically conductive ribbon includes a roughened surface. An insulating encapsulation is molded onto the semiconductor die and the electrically conductive ribbon. The roughened surface of the electrically conductive ribbon provides a roughened coupling interface to the insulating encapsulation.

A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques.

The on-resistance of a semiconductor device is reduced. A package structure composing the semiconductor device includes a die pad, a plurality of leads, a first semiconductor chip having a power transistor and mounted on the die pad, and a second semiconductor chip including a control circuit for controlling the power transistor and mounted on the first semiconductor chip. Here, a source pad of the first semiconductor chip is electrically connected to a first lead and a seventh lead of the plurality of leads via a clip made of a material which is copper as a main component, and the width (and cross-sectional area) of the clip is larger than the width (and diameter) of a wire in plan view.

Semiconductor module including a semiconductor and including a shaped metal body that is electrically contacted by the semiconductor, for forming a contact surface for an electrical conductor, wherein the shaped metal body is bent or folded. A method is also described for establishing electrical contacting of an electrical conductor on a semiconductor, said method including the steps of: fastening a bent or folded shaped metal body of a constant thickness to the semiconductor by means of a first fastening method and then fastening the electrical conductor to the shaped metal body by means of a second fastening method.

A clip-bonded semiconductor package including: a semiconductor die including a bond pad on a top side of the semiconductor die, the bond pad is arranged to receive a bond clip, the bond clip is also arranged to provide electrical connection to the bond pad via a connection part of the bond clip, the bond clip further includes a buffer layer provided to at least the connection part. A hardness of a material of the buffer layer is lower than a hardness of a material of the bond clip.