The present disclosure relates to a power module. The power module includes a first die having an upper surface; a second die adjacent to the first die and having an upper surface at an elevation different from the upper surface of the first die; a circuit structure disposed over the first die and the second die and having a surface; and an elastic structure connecting the first die and the second die to the first circuit structure and configured to keep the surface of the circuit structure being substantially horizontal.

The purpose of this invention is to provide a semiconductor device that prevents defects in semiconductor elements caused by differences in thermal expansion and maintains low electrical resistance by directly or indirectly laminating an FeNi alloy metal layer onto the front-surface or back-surface electrodes of the semiconductor element. In this invention, an FeNi alloy metal layer is directly or indirectly applied on the surface electrodes of the semiconductor element, and the semiconductor element is connected to a conductor through the FeNi alloy metal layer. Depending on the application, the Ni content of the FeNi alloy metal layer is set within the range of 36% to 45% by weight, and the thickness of the FeNi alloy metal layer is set within the range of 2 m to 20 m.

A semiconductor device according to the present disclosure includes: a lead frame having a plurality of die pad portions electrically independent from each other; a power semiconductor element provided on each of the die pad portions; a wire electrically connecting the power semiconductor element and the lead frame; an epoxy-based resin provided on at least a part of the lead frame; and a sealing resin covering at least each of the die pad portions, the power semiconductor element, the wire, and the epoxy-based resin.

A power module includes: a first substrate having an outer surface and an inner surface; a semiconductor die coupled to the inner surface of the first substrate; a second substrate having an outer surface and an inner surface, the semiconductor die being coupled to the inner surface of the second substrate; and a flex circuit coupled to the semiconductor die.

An electrical power module includes a base plate, including an electrically isolating substrate and a first metallic layer formed on a first side of the electrically isolating substrate. The electrical power module also includes electrical connection pillars extending from the first metallic layer. The electrical power module further includes at least one encapsulant retention feature extending from the first metallic layer and including at least one surface that is angled or parallel relative to the first side of the electrically isolating substrate and faces the first side of the electrically isolating substrate. The electrical power module additionally includes at least one electrical component electrically coupled with the metallic layer of the base plate. The electrical power module further includes an encapsulant encapsulating the at least one electrical component, the metallic layer, and the at least one encapsulant retention feature and partially encapsulating the electrical connection pillars.

A method of making an electronics package for an electrical power module includes positioning a base plate into an electrolyte solution such that a first metallic layer of the base plate directly contacts the electrolyte solution. The method also includes positioning a deposition anode array into the electrolyte solution such that a gap is established between the first metallic layer and the deposition anode array. The method further includes connecting the first metallic layer to a power source and connecting the deposition anode array to the power source. The method also includes transmitting electrical energy from the power source through the deposition anode array, through the electrolyte solution, and to the first metallic layer, such that material is deposited onto the first metallic layer and forms an electrical connection pillar, an electrical-component retention feature, and an encapsulant retention feature of the electronics package.

A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

Embodiments of the present disclosure relate to a semiconductor package, a method of forming the package and an electronic device. For example, the semiconductor package may comprise a first substrate assembly comprising a first surface and a second surface opposite the first surface. The semiconductor package may also comprise one or more chips connected or coupled to the first surface of the first substrate assembly by a first thermally and electrically conductive connecting material. In addition, the semiconductor package further comprises a second substrate assembly comprising a third surface and a fourth surface opposite the third surface, the third surface and the first surface being arranged to face each other, and the third surface being connected to one or more chips by a second thermally and electrically conductive connecting material. At least one of the first surface and the third surface is shaped to have a stepped pattern to match a surface of the one or more chips. Embodiments of the present disclosure may at least simplify the double-sided heat dissipation structure and improve the heat dissipation effect of the chip.

A semiconductor device includes a power semiconductor element, and a molding resin sealing the power semiconductor element. In plan view, the molding resin has a rectangular shape consisting of a first side and a second side extending along a first direction, and a third side and a fourth side extending along a second direction orthogonal to the first direction. The first side is longer than the third side. The molding resin is provided with a first threaded bore and a second threaded bore, the first threaded bore and the second threaded bore penetrating the molding resin along a third direction orthogonal to the first direction and the second direction.

A thin-film resistor (TFR) includes conductive line(s) and a resistive layer over the conductive line(s). The TFR also includes at least one viabar structure coupled to the resistive layer and including a first viabar portion electrically connected to the resistive layer at an edge thereof and a second viabar portion electrically connected to the conductive line(s). In other cases, a viabar structures partially land over the resistive layer and are electrically connected to an edge of the resistive layer and partially land on the conductive line(s). Among other advantages, the viabar structure reduces current crowding from tight contact spacing, and allows alternative routing of interconnects to the TFR.