H10W72/07323

Package structure and method of fabricating the same

A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

Manufacturing apparatus and manufacturing method of semiconductor device
12563999 · 2026-02-24 · ·

A manufacturing apparatus of a semiconductor device includes: a stage; a bonding head, including a mounting tool, a tool heater, and a lifting and lowering mechanism; and a controller performing bonding processing. The controller performs, in the bonding processing: first processing in which, after a chip is brought into contact with a substrate, as heating of the chip is started, the chip is pressurized against the substrate; distortion elimination processing in which, after the first processing and before melting of a bump, the lifting and lowering mechanism is driven in a lifting direction, thereby eliminating distortion of the bonding head; and second processing in which, after the distortion elimination processing, position control is performed on the lifting and lowering mechanism so as to cancel thermal expansion and contraction of the bonding head, thereby maintaining a gap amount at a specified target value.

Method of forming wafer-to-wafer bonding structure

A method of forming a semiconductor structure is provided. Two wafers are first bonded by oxide bonding. Next, the thickness of a first wafer is reduced using an ion implantation and separation approach, and a second wafer is thinned by using a removal process. First devices are formed on the first wafer, and a carrier is then attached over the first wafer, and an alignment process is performed from the bottom of the second wafer to align active regions of the second wafer for placement of the second devices with active regions of the first wafer for placement of the first devices. The second devices are then formed in the active regions of the second wafer. Furthermore, a via structure is formed through the first wafer, the second wafer and the insulation layer therebetween to connect the first and second devices on the two sides of the insulation layer.