A package structure includes a first dielectric layer disposed on a first patterned circuit layer, a first conductive via in the first dielectric layer and electrically connected to the first patterned circuit layer, a circuit layer on the first dielectric layer, a second dielectric layer on the first dielectric layer and covering the circuit layer, a second patterned circuit layer on the second dielectric layer and including conductive features, a chip on the conductive features, and a molding layer disposed on the second dielectric layer and encapsulating the chip. The circuit layer includes a plurality of portions separated from each other and including a first portion and a second portion. The number of pads corresponding to the first portion is different from that of pads corresponding to the second portion. An orthographic projection of each portion overlaps orthographic projections of at least two of the conductive features.

Integrated circuit structures having deep via structures, and methods of fabricating integrated circuit structures having deep via structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure. A conductive via is vertically beneath and extends into the conductive trench contact structure. The conductive via has a first width beneath the epitaxial source or drain structure less than a second width laterally adjacent to the epitaxial source or drain structure.

A semiconductor device is provided. The semiconductor device includes: a first substrate; an active pattern extending on the first substrate; a gate electrode extending on the active pattern; a source/drain region on the active pattern; a first interlayer insulating layer on the source/drain region; a sacrificial layer on the first substrate; a lower wiring layer on a lower surface of the sacrificial layer; a through via trench extending to the lower wiring layer by passing through the first interlayer insulating layer and the sacrificial layer in a vertical direction; a through via inside the through via trench and connected to the lower wiring layer; a recess inside the sacrificial layer and protruding from a sidewall of the through via trench in the second horizontal direction; and a through via insulating layer extending along the sidewall of the through via trench and into the recess.

A semiconductor device includes a substrate having a first main surface and a second main surface opposite to the first main surface, and a first conductive layer including a first metal layer and a second metal layer, the first metal layer covering the second main surface, the second metal layer covering the first metal layer and including dendrites, wherein a via hole extending through the substrate and having an inner wall surface is formed in the substrate, and wherein the first metal layer, which is covered with the second metal layer, covers the inner wall surface.

Provided is a backside power distribution network (BSPDN) semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device including an active device that includes an epitaxial layer, a second semiconductor device provided on a second surface of the wafer opposite to the first surface, the second semiconductor device including a power rail configured to supply power, and a through-silicon via (TSV) protruding from the power rail and extending to a level of the epitaxial layer of the active device.

An integrated circuit device includes a substrate, having a front surface and a rear surface opposite to each other, and a fin-type active region defined by a trench in the front surface, a device separation layer filling the trench, a source/drain region on the fin-type active region, a first conductive plug arranged on the source/drain region and electrically connected to the source/drain region, a power wiring line at least partially arranged on a lower surface of the substrate, a buried rail connected to the power wiring line through the device separation layer and decreasing in horizontal width toward the power wiring line, and a power via connecting the buried rail to the first conductive plug.

Disclosed herein are methods for direct bonding. In some embodiments, the direct bonding method includes microwave annealing a dielectric bonding layer of a first element by exposing the dielectric bonding layer to microwave radiation and then directly bonding the dielectric bonding layer of the first element to a second element without an intervening adhesive. The bonding method also includes depositing the dielectric bonding layer on a semiconductor portion of the first element at a first temperature and microwave annealing the dielectric bonding layer at a second temperature lower than the first temperature.

A microelectronic structure including a nanosheet transistor that includes a source/drain. A frontside contact that includes a first section located on the frontside of the source/drain and a via section that extends to the backside of the nanosheet transistor. A shallow isolation layer located around a portion of the via section the first frontside contact. A backside metal line located on a backside surface of the via section and located on a backside surface of the shallow trench isolation layer. A dielectric liner located along a sidewall of the backside metal line and located along a bottom surface of the backside metal line.

A method of forming a semiconductor device is provided. The method includes forming an etch stop layer on a substrate having a first thickness, forming an epitaxial layer on the etch stop layer, and forming a wafer device on the epitaxial layer. The wafer device is bonded to a bonding wafer using hybrid bonding. The substrate is then ground to a second thickness less than the first thickness and planarized to a third thickness less than the second thickness. A mask layer is deposited on a bottom surface of the etch stop layer, and at least one via opening is formed in the mask layer. The etch stop layer is selectively removed, and the mask layer is removed to expose the substrate at the third thickness.

A semiconductor device includes a semiconductor substrate having a top surface and a bottom surface. An electronic device is integrated into the top surface of the semiconductor substrate. A conductive power rail is positioned intermediate the top surface and the bottom surface of the semiconductor substrate. The conductive power rail is configured to conduct power to the electronic device.