A metal interconnect structure is doped with zinc, indium, or gallium using top-down doping processes to improve diffusion barrier properties with minimal impact on line resistance. Dopant is introduced prior to metallization or after metallization. Dopant may be introduced by chemical vapor deposition on a liner layer at an elevated temperature prior to metallization, by chemical vapor deposition on a metal feature at an elevated temperature after metallization, or by electroless deposition on a copper feature after metallization. Application of elevated temperatures causes the metal interconnect structure to be doped and form a self-formed barrier layer or strengthen an existing diffusion barrier layer.

A light-emitting substrate and a manufacturing method thereof are provided. The reactivity of part of the ink layer outside the preset area that is far from the light with the first preset wavelength is improved by a heating process. Thus, the part of the ink layer reacts sufficiently under irradiation of the light with the first preset wavelength at lower energy. This improves an undercut issue caused by insufficient curing of the ink layer outside the preset area far from the light with the first preset wavelength, thereby preventing the ink layer from being peeled off from the light-emitting substrate.

A metal interconnect structure is doped with zinc, indium, or gallium using top-down doping processes to improve diffusion barrier properties with minimal impact on line resistance. Dopant is introduced prior to metallization or after metallization. Dopant may be introduced by chemical vapor deposition on a liner layer at an elevated temperature prior to metallization, by chemical vapor deposition on a metal feature at an elevated temperature after metallization, or by electroless deposition on a copper feature after metallization. Application of elevated temperatures causes the metal interconnect structure to be doped and form a self-formed barrier layer or strengthen an existing diffusion barrier layer.

A semiconductor structure includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first via structure in a first dielectric layer, the first via structure including a first contact via surface. At least a portion of the first via structure is in direct contact with the first dielectric layer. The second semiconductor structure includes a second via structure in a second dielectric layer, the second via structure including a second contact via surface. At least a portion of the second via structure is in direct contact with the second dielectric layer. The first contact via surface is bonded with the second contact via surface. The second contact via surface and the first contact via surface have an overlapping interface in the vertical direction. A first barrier layer is formed at a non-overlapping interface in the first contact via surface and the second contact via surface. The first barrier layer contains a multi-component oxide.

An apparatus includes a backside supporting layer having a first thickness, an adhesive layer over the backside supporting layer, a metal layer over the adhesive layer, wherein the metal layer functions as a backside connector, a semiconductor substrate layer over the metal layer, wherein the semiconductor substrate active layer has a second thickness, and a plurality of front side connectors, wherein active circuits in the semiconductor substrate layer over are electrically coupled between the plurality of front side connectors and the metal layer.