Patent classifications
H10P52/40
Polishing composition, polishing method, and method of manufacturing semiconductor substrate
Provided is a means capable of polishing an organic material at a high polishing speed and reducing the number of scratches after polishing. The polishing composition of the present invention contains zirconia particles and a dispersing medium, in which the zirconia particles contain at least one of tetragonal zirconia and cubic zirconia, and an average secondary particle size of the zirconia particles is less than 80 nm.
Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes forming a gate oxide layer on a substrate, where the substrate includes a high voltage region and a low voltage region. The gate oxide layer is disposed in the high voltage region. Wet etching is performed on the gate oxide layer to reduce a thickness of the gate oxide layer. Multiple trenches are formed around the high voltage region in the substrate, where forming the trenches includes removing an edge of the gate oxide layer to make the thickness of the gate oxide layer uniform. An insulating material is filled in the trenches to form multiple shallow trench isolation structures, where an upper surface of the shallow trench isolation structures close to the edge of the gate oxide layer is coplanar with an upper surface of the gate oxide layer.
DIAMOND-BASED POLISHING COMPOSITIONS WITH IMPROVED SILICON CARBIDE REMOVAL RATE
Provided is a polishing composition for polishing semiconductor wafer surfaces, including a surface-modified monocrystalline diamond with a D(50) particle size ranging from about 0.10 m to about 1 m; a vehicle selected from the group consisting of water-based vehicles, glycol-based vehicles, oil-based vehicles, and hydrocarbon-based vehicles; and optionally one or more additives. Further presented are associated methods for polishing semiconductor wafer surfaces.
Inverting wafer and etching back plane to expose conductive pillars from back plane of wafer for further processing
A semiconductor structure, a method for preparing the semiconductor structure and a memory are provided. The method includes: providing a wafer in which multiple conductive pillars are formed; inverting the wafer and performing etching on a back plane of the wafer to expose each conductive pillar from the back plane of the wafer, and lengths of the multiple conductive pillars exposed to the back plane are different; depositing an insulation layer on the back plane of the wafer and the conductive pillars, and depositing a filling layer on the insulation layer, the filling layer completely covering back ends of the multiple conductive pillars; and performing polishing on the filling layer and back ends of a part of the conductive pillars, until a back end of each conductive pillar is exposed and the back ends of the multiple conductive pillars are flush with a back plane of the filling layer.
SEMICONDUCTOR DEVICE HAVING A THROUGH VIA
A semiconductor device includes a substrate. The semiconductor device further includes a gate structure extending along a first direction. The semiconductor device further includes a first source/drain (S/D) region. The semiconductor device further includes a second S/D region separated from the first S/D region in the first direction. The semiconductor device further includes a backside via extending through the substrate, wherein the backside via is between the first S/D region and the second S/D region. The semiconductor device further includes a silicide layer between a sidewall of the first S/D region and the backside via, wherein the backside via contacts the silicide layer. The semiconductor device further includes a first dielectric spacer between the backside via and the second S/D region, wherein the backside via contacts the first dielectric spacer.
SYSTEM AND METHOD FOR MONITORING CHEMICAL MECHANICAL POLISHING
An apparatus for chemical mechanical polishing of a wafer includes a process chamber and a rotatable platen disposed inside the process chamber. A polishing pad is disposed on the platen and a wafer carrier is disposed on the platen. A slurry supply port is configured to supply slurry on the platen. A process controller is configured to control operation of the apparatus. A set of microphones is disposed inside the process chamber. The set of microphones is arranged to detect sound in the process chamber during operation of the apparatus and transmit an electrical signal corresponding to the detected sound. A signal processor is configured to receive the electrical signal from the set of microphones, process the electrical signal to enable detection of an event during operation of the apparatus, and in response to detecting the event, transmit a feedback signal to the process controller. The process controller is further configured to receive the feedback signal and initiate an action based on the received feedback signal.
Methods for polishing bulk silicon devices
Methods for polishing bulk silicon are disclosed. In one aspect, mechanical polishing is facilitated by cyclically alternating between a silicon reactive slurry and deionized water while a mechanical polishing head operates on a surface. In exemplary aspects, the polishing head is polishing a bulk silicon carrier wafer to expose a backside of a radio frequency (RF) complementary metal oxide semiconductor (CMOS) switch, although other semiconductors may also benefit from exemplary aspects of the present disclosure. While the silicon slurry is present, a reaction between the bulk silicon and the slurry takes place allowing the polishing head to remove the bulk silicon. The deionized water interrupts this reaction and helps prevent overpolishing which might otherwise damage the device.
Methods of Forming Interconnect Structures in Semiconductor Fabrication
A semiconductor structure includes a first dielectric layer, a first via and a second via disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer, the first via, and the second via, a first conductive line disposed on the first via and in a bottom portion of the second dielectric layer, a second conductive line disposed on the second via and in the bottom portion of the second dielectric layer, a first barrier layer extending along sidewalls and a top surface of the first conductive line, and a second barrier layer extending along sidewalls and a top surface of the second conductive line. The bottom portion of the second dielectric layer includes an air gap between the first conductive line and the second conductive line.
POLISHING AGENT, POLISHING METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR COMPONENT, ADDITIVE SOLUTION FOR POLISHING AGENT, AND METHOD FOR MANUFACTURING ADDITIVE SOLUTION FOR POLISHING AGENT
A polishing agent with excellent pH stability, an additive solution for a polishing agent for preparing the polishing agent and a method for manufacturing the same, a polishing method capable of performing high-speed polishing, and a method for manufacturing a semiconductor component using the polishing method are provided. A polishing agent contains (bi)carbonate of a primary amine, a secondary amine, a tertiary amine, or a quaternary ammonium, and water, in which an organic group that the amine or the ammonium has is a group selected from a linear alkyl group, a branched alkyl group, and an alkanol group, a content of the (bi)carbonate is 5 mmol/L to 130 mmol/L based on the whole polishing agent, a boiling point of the amine or the ammonium is 0 C. to 500 C., and pH is 7 to 11.