A semiconductor arrangement and method of forming the semiconductor arrangement are provided. The semiconductor arrangement includes a device having a first surface and a second surface opposite the first surface. A first through substrate via (TSV) structure extends between the first surface and the second surface in a first region of the device. A second TSV structure extends between the first surface and the second surface in a second region of the device. The first TSV structure has a first cross-sectional area. The second TSV structure has a second cross-sectional area greater than the first cross-sectional area.

An apparatus and method for efficiently routing power signals across a semiconductor die. In various implementations, an integrated circuit includes, at a first node that receives a power supply reference, a first micro through silicon via (TSV) that traverses through a silicon substrate layer to a backside metal layer. The integrated circuit includes, at a second node that receives the power supply reference, a second micro TSV that physically contacts at least one source region. The integrated circuit includes a first power rail that connects the first micro TSV to the second micro TSV. This power rail replaces contacts between the micro TSVs and a second power rail such as the frontside metal zero (M0) layer. Each of the first power rail, the second power rail, and the backside metal layer provides power connection redundancy that increases charge sharing, improves wafer yield, and reduces voltage droop.

An integrated circuit (IC) chip is provided. In one aspect, a semiconductor substrate includes active devices at its front surface and power delivery tracks on its back surface. The active devices are powered through mutually parallel buried power rails, with the power delivery tracks running transversely with respect to the power rails, and connected to the power rails by a plurality of Through Semiconductor Via connections, which run from the power rails to the back of the substrate. The TSVs are elongate slit-shaped TSVs aligned to the power rails and arranged in a staggered pattern, so that any one of the power delivery tracks is connected to a first row of mutually parallel TSVs, and any power delivery track directly adjacent to the power delivery track is connected to another row of TSVs which are staggered relative to the TSVs of the first row. A method of producing an IC chip includes producing the slit-shaped TSVs before the buried power rails.

Techniques for signal routing between a host and dynamic random-access memory (DRAM) are provided. In an example, a routing layer for a dynamic random-access memory die (DRAM can include multiple through silicon via (TSV) terminations configured to electrically couple with TSVs of the DRAM, an intermediate interface area, and multiple routing traces. the multiple TSV terminations can be arranged in multiple TSV areas. The multiple TSV areas can be arranged in two columns. The intermediate interface area can include multiple micro-pillar bump terminations configured to couple, via a micro-pillar bump, with corresponding micro-pillar bump terminations of a semiconductor interposer. The multiple routing traces can couple control TSV terminations of the multiple TSV areas with a corresponding micro-pillar bump termination of the intermediate interface.