Integrated circuit devices are provided. An integrated circuit device includes an insulating layer and a metal via structure that is in the insulating layer. The metal via structure has a lower portion and an upper portion that is narrower than the lower portion. Moreover, the integrated circuit device includes a metal line that is on and electrically connected to the metal via structure. Related methods of forming integrated circuit devices are also provided.

A connecting structure includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants.

A metallic stack and a preparing method therefor, and an electronic device including the metallic stack. The metallic stack includes at least one interconnection wire layer and at least one via layer alternately arranged on a substrate. At least one pair of interconnection wire layer and via layer in the metallic stack includes interconnection wires in the interconnection wire layer and conductive vias in the via layer, wherein the interconnection wire layer is closer to the substrate than the via layer. At least a part of the interconnection wires is integrated with the conductive vias on the at least a part of the interconnection wires.

A semiconductor structure includes a semiconductor substrate, a dielectric layer, a via, a first graphene layer, and a metal line. The dielectric layer is over the semiconductor substrate. The via extends through the dielectric layer. The first graphene layer extends along a top surface of the via. The metal line spans the first graphene layer. The metal line has a line width decreasing as a distance from the first graphene layer increases.

A layer of conductive material is formed above a bottom-most layer of interconnect structures in an interconnect layer of a semiconductor device, and the layer of conductive material is etched to define the bottom-most layer of metallization structures from the layer of conductive material. To reduce the likelihood of collapse of the free-standing metallization structures, the exposed sidewall surfaces of the free-standing metallization structures may be oxidized to form metal-oxide sidewalls for the free-standing metallization structures. The metal-oxide sidewalls may be formed using a self-aligned oxidation technique that specifically targets the sidewalls of the free-standing metallization structures for oxidation. The metal-oxide sidewalls may be formed of a metal-oxide material that increases the mechanical strength of the free-standing metallization structures, which enables the free-standing metallization structures to resist collapsing.

An interconnect structure including a dielectric structure, plugs, and conductive lines is provided. The dielectric structure is disposed on a substrate. The plugs are disposed in the dielectric structure. The conductive lines are disposed in the dielectric structure and are electrically connected to the plugs. The sidewall of at least one of the conductive lines is in direct contact with the dielectric structure.

Various embodiments of interconnect structures and methods of forming interconnect structures used in an integrated circuit (IC) device are provided in the present disclosure. More specifically, techniques are provided for forming low-resistivity interconnect structures including a multilayer interconnect film stack comprising a first conductive film formed beneath and in contact with a second conductive film. The presence of the first conductive film within the multilayer interconnect film stack decreases the resistivity of the second conductive film when the second conductive film is deposited onto the first conductive film to provide a low-resistivity interconnect structure.