A physically unclonable function (PUF) device includes capacitor array couple to an electronic device. The capacitor array includes a plurality of parallel conductive elements coupled to a dielectric material having a spatially varying permittivity to define array of randomly valued capacitors.

A physical unclonable function (PUF) generator structure including a substrate and a PUF generator is provided. The PUF generator includes a first electrode layer, a second electrode layer, a first dielectric layer, a first contact, a second contact, and a third contact. The first electrode layer is disposed on the substrate. The second electrode layer is disposed on the first electrode layer. The first dielectric layer is disposed between the first electrode layer and the second electrode layer. The first contact and the second contact are electrically connected to the first electrode layer and are separated from each other. The third contact is electrically connected to the second electrode layer.

A semiconductor device includes a memory cell randomly presenting a first logic state or a second logic state and formed on a first side of a substrate, and a first and a second bit lines formed on a second side of the substrate opposite to the first side. The memory cell includes: a programming transistor having a first and a second source/drain terminals; a first reading transistor having a first source/drain terminal coupled to the first source/drain terminal of the programming transistor; and a second reading transistor having a first source/drain terminal coupled to the second source/drain terminal of the programming transistor. The first bit line is operatively coupled to a second source/drain terminal of the first reading transistor, and the second bit line is operatively coupled to a second source/drain terminal of the second reading transistor.

A system may include an integrated circuit (IC) package. The IC package may include one or more IC die hosting one or more circuits, and an interposer. The interposer may be coupled to the one or more IC die via an interconnection layer. The interposer may include one or more electrically active devices configured to provide one or more security functions to secure the one or more circuits. The interposer may be coupled to a backside power of the IC package. In some embodiments, the backside power of the IC package may include one or more backside power delivery networks.

A system may include an integrated circuit (IC) package. The IC package may include one or more IC die hosting one or more circuits, and an interposer. The interposer may be coupled to the one or more IC die via an interconnection layer. The interposer may include one or more electrically active devices configured to provide one or more security functions to secure the one or more circuits. The interposer may be coupled to a backside power of the IC package. In some embodiments, the backside power of the IC package may include one or more backside power delivery networks.

A disclosed chip structure includes a coded pattern of dummy fill shapes with steganographically embedded information. The coded pattern is in a specific area of the chip, is a modified instance of a known pattern, and is decodable into a binary integer based on observable differences between the coded pattern and the known pattern at corresponding locations with the patterns. The location of the specific area containing the coded pattern, the decode cipher and the binary integer can be maintained as proprietary information (e.g., by a technology company or semiconductor foundry). Chip authentication can be made by a party with the proprietary information. Alternatively, the binary integer could be a means of conveying confidential information to a party that has been provided with the decode cipher and the location of the specific area containing the coded pattern. Also disclosed are system and method embodiments for designing and manufacturing the chip.

A disclosed chip structure includes a coded pattern of dummy fill shapes with steganographically embedded information. The coded pattern is in a specific area of the chip, is a modified instance of a known pattern, and is decodable into a binary integer based on observable differences between the coded pattern and the known pattern at corresponding locations with the patterns. The location of the specific area containing the coded pattern, the decode cipher and the binary integer can be maintained as proprietary information (e.g., by a technology company or semiconductor foundry). Chip authentication can be made by a party with the proprietary information. Alternatively, the binary integer could be a means of conveying confidential information to a party that has been provided with the decode cipher and the location of the specific area containing the coded pattern. Also disclosed are system and method embodiments for designing and manufacturing the chip.