A semiconductor device includes a substrate that comprises a first region and a second region; a first wiring structure on the first region of the substrate, wherein the first wiring structure comprises a lower bonding pad; a second wiring structure on the first wiring structure, wherein the second wiring structure comprises an upper bonding pad that contacts the lower bonding pad; a lower alignment pattern on the second region of the substrate, wherein the lower alignment pattern is spaced apart from the lower bonding pad; and an upper alignment pattern on the second region of the substrate, wherein the upper alignment pattern is spaced apart from the upper bonding pad, wherein the lower alignment pattern comprises sub-lower alignment patterns, and wherein the upper alignment pattern comprises sub-upper alignment patterns.

A chip package includes a semiconductor substrate, a conductive pad, an isolation layer, and a redistribution layer. The semiconductor substrate has a first surface, a second surface facing away from the first surface, a through hole through the first and second surfaces, and a recess in the first surface. The conductive pad is located on the second surface of the semiconductor substrate and in the through hole. The isolation layer is located on the second surface of the semiconductor substrate and surrounds the conductive pad. The redistribution layer is located on the first surface of the semiconductor substrate, and extends into the recess, and extends onto the conductive pad in the through hole.

A wafer-level package includes a first integrated circuit die having pads on its front side and a second integrated circuit die having pads on its front side, with a back side of the second die attached to the front side of the first die by an adhesive layer. A resin layer containing an activatable catalyst material is disposed across the front side of the first die, along edge sides of the second die, and across the front side of the second die. Selected portions of the resin layer are activated by laser radiation and metallized to form a redistribution layer providing electrical interconnection between the dies. A solder resist layer is formed over the resin layer, and solder balls are connected to metallized portions of the redistribution layer. The laser-direct-structuring process enables formation of conductive interconnects extending over die edges without conventional drilling or photo-patterning.

A display device includes a display area and a non-display area which is adjacent to the display area, a pad in the non-display area and connected to the display area, and an insulating layer on the pad. A portion of the pad is exposed outside of the insulating layer to define an exposed portion of the pad, the insulating layer includes a first portion having a first thickness and a second portion having a second thickness which is less than the first thickness, and the second portion of the insulating layer is between the exposed portion of the pad and the first portion of the insulating layer.

In a described example, an apparatus includes a transistor formed on a semiconductor substrate, the transistor including: a transistor gate and an extended drain between the transistor gate and a transistor drain contact; a transistor source contact coupled to a source contact probe pad; a first dielectric layer covering the semiconductor substrate and the transistor gate; a source field plate on the first dielectric layer and coupled to a source field plate probe pad spaced from and electrically isolated from the source contact probe pad; and the source field plate capacitively coupled through the first dielectric layer to a first portion of the extended drain.

A semiconductor package includes a silicon substrate including a plurality of through openings, and a redistribution wiring layer including a first surface and a second surface opposite the first surface, the second surface facing the silicon substrate, the redistribution wiring layer including a first pad area and a second pad area. The redistribution wiring layer includes a plurality of bonding pads on the first pad area at the first surface, a plurality of test pads on the second pad area at the first surface, a plurality of landing pads on the second pad area at the second surface, the plurality of landing pads in communication with the plurality of through openings, respectively, and a plurality of redistribution wires electrically connected to the plurality of bonding pads and the plurality of landing pads.