An electronic device, includes: (i) a processing chiplet configured to process data and having a first side and a second side, (ii) one or more first static random-access memory (SRAM) chiplets disposed on the first side of the processing chiplet and configured to store a first portion of the data, (iii) one or more second SRAM chiplets disposed on the second side of the processing chiplet and configured to store a second portion of the data, (iv) one or more first electrical terminals disposed on the first side of the processing chiplet and configured to electrically connect between the first side of the processing chiplet and the first SRAM chiplets, and (v) one or more second electrical terminals disposed on the second side of the processing chiplet and configured to electrically connect between the second side of the processing chiplet and the second SRAM chiplets.

A semiconductor package structure includes a memory stack, a substrate, a processor die, and a liquid cooling structure. The memory stack includes a plurality of semiconductor dies horizontally separate with each other, wherein each semiconductor die has a top surface, a bottom surface, and four sidewalls, wherein the second sidewall is opposite to the first sidewall. A plurality of edge pads are arranged on the first sidewall of each semiconductor die. The substrate is under the memory stack and electrically connected to the plurality of edge pads of each of the semiconductor dies. The processor die is over the substrate and adjacent to the memory stack. The liquid cooling structure is over the memory stack and the processor die, and thermally coupled to both the memory stack and the processor die via the second sidewall of each of the semiconductor dies and the top surface of the processor die.

A semiconductor package may include a package substrate including first and second surfaces, which are opposite to each other, a first semiconductor chip on the first surface, a first mold layer on the first surface of the package substrate and top and side surfaces of the first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on the second surface, a second mold layer on the second surface of the package substrate, bottom and side surfaces of the second semiconductor chip, and bottom and side surfaces of the third semiconductor chip, a vertical conductive pillar provided to penetrate the second mold layer in a vertical direction and horizontally spaced apart from the second and third semiconductor chips, and connection terminals between a bottom surface of the first semiconductor chip and the first surface. The vertical conductive pillar may be placed on the second surface.