Patent classifications
H10W20/051
SEMICONDUCTOR DEVICE WITH ISOLATION STRUCTURE AND METHOD FOR FABRICATING THE SAME
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a plurality of through-substrate vias (TSVs), a plurality of insulating segments, and a plurality of liners. The substrate includes a first surface and a second surface opposite to the first surface. The plurality of TSVs penetrate through the substrate. Each of the insulating segments includes an embedded portion disposed in the TSV, and an extension portion disposed over the embedded portion and the first surface. The liner is disposed on a side surface of the TSV and between the side surface and the embedded portion of the insulating segment. The plurality of insulating segments and the plurality of liners are exposed by the second surface of the substrate.
SEMICONDUCTOR DEVICE WITH ISOLATION STRUCTURE AND METHOD FOR FABRICATING THE SAME
The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a plurality of through-substrate vias (TSVs), a plurality of insulating segments, and a plurality of liners. The substrate includes a first surface and a second surface opposite to the first surface. The plurality of TSVs penetrate through the substrate. Each of the insulating segments includes an embedded portion disposed in the TSV, and an extension portion disposed over the embedded portion and the first surface. The liner is disposed on a side surface of the TSV and between the side surface and the embedded portion of the insulating segment. The plurality of insulating segments and the plurality of liners are exposed by the second surface of the substrate.
3D NAND memory device with isolation trenches and fabrication method thereof
The present disclosure discloses a semiconductor device and a fabrication method thereof. In the method, firstly etching a substrate in a first device region to form at least one first trench and then etching the substrate in both first device region and second device region to form at least one first isolation trench at the positions corresponding to the at least one first trench and form at least one second isolation trench in the second device region. Herein a depth of the first isolation trench is larger than that of the second isolation trench.