A transistor having a GaN stack on a substrate, an AlGaN barrier layer on the GaN stack, a gate stack including a p-GaN layer on the AlGaN barrier layer, a dielectric layer on a first portion of the p-GaN layer, and a gate electrode on the dielectric layer, and an AlGaN cap layer on a second portion of the p-GaN layer and laterally outward of a portion of the gate electrode. A method of fabricating a semiconductor device includes forming a dielectric layer on a patterned p-GaN layer and forming a gate electrode on the dielectric layer.

Semiconductor devices including an interspersed gate structure are described. In one example, a semiconductor device comprises a semiconductor substrate including a source region, a gate region, a drain region, and a drain access region, where a heterojunction structure is disposed over the semiconductor substrate. The heterojunction structure includes a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer. A p-doped III-N layer is disposed over the barrier layer in the gate region, where the p-doped III-N layer may contain a concentration profile of an element with one or more peaks at different distances from a surface of the p-doped III-N layer.

We provide a fabrication process for III-nitride devices. An iridium structure is deposited and then oxidized at high temperature (700 C. or more) to form an iridium oxide Schottky contact to a III-nitride. This IrO.sub.x contact is then protected with a passivation structure. Such contacts have various device applications, such as forming Schottky diodes and acting as a gate in a transistor or 2D electron gas structure.