Patent classifications
H
H10
H10W
20/00
H10W20/0886
Interconnects including graphene capping and graphene barrier layers
12543550
·
2026-02-03
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A semiconductor structure includes a semiconductor substrate, a dielectric layer, a via, a first graphene layer, and a metal line. The dielectric layer is over the semiconductor substrate. The via extends through the dielectric layer. The first graphene layer extends along a top surface of the via. The metal line spans the first graphene layer. The metal line has a line width decreasing as a distance from the first graphene layer increases.