Patent classifications
H10W20/4435
Interconnects including graphene capping and graphene barrier layers
A semiconductor structure includes a semiconductor substrate, a dielectric layer, a via, a first graphene layer, and a metal line. The dielectric layer is over the semiconductor substrate. The via extends through the dielectric layer. The first graphene layer extends along a top surface of the via. The metal line spans the first graphene layer. The metal line has a line width decreasing as a distance from the first graphene layer increases.
INTERCONNECT STRUCTURE HAVING METAL FEATURES WITH DIFFERENT VOLUME AND MATERIALS, AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing an interconnect structure includes: forming a base structure; forming a first metal feature on the base structure, the first metal feature having a first volume and including a first metallic material; forming a first dielectric layer surrounding the first metal feature and over the base structure; and forming a second metal feature in the first dielectric layer, the second metal feature being spaced apart from the first metal feature, having a second volume greater than the first volume, and including a second metallic material different from the first metallic material.