Patent classifications
H10D64/01322
INTEGRATED CIRCUIT DEVICE WITH GATE ANTI-TYPE DOPED REGION
Some embodiments relate to an integrated circuit (IC) device that includes a substrate including a P-well region and a dielectric structure. The dielectric structure is disposed at a surface of the substrate, extends downward into the substrate, and is located at a lateral perimeter of the P-well region. The IC device further includes a dielectric layer disposed over the P-well region and extends laterally over the dielectric structure. The IC device also includes an N+ gate structure disposed over the dielectric layer and includes at least one P+ region located over the P-well region of the substrate and the dielectric structure.
Methods for pre-deposition treatment of a work-function metal layer
A method for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.