Patent classifications
H10W72/324
CHIP PACKAGING STRUCTURE AND PREPARATION METHOD
A chip packaging structure includes, a chip on a substrate; an enclosure structure on the chip, a wall of the enclosure structure comprises a sealed cavity, and the chip is revealed through the sealed cavity; a layer of thermal interface material for the chip, formed by filling a liquid metal into the sealed cavity of the wall of the enclosure structure; and a heat sink, formed on the layer of thermal interface material, is hermetically sealed to the wall of the enclosure structure. The heat sink component is formed on the layer of the thermal interface material, sealed and connected to the enclosure structure. The enclosure structure using flexible materials to prevent the liquid metal from overflowing in the encapsulation and application process, thereby reducing degradation. The UV curing adhesive is used for sealing and fixing the connection to the thermal interface material layer, so the disassembly and replacement of the process is simpler.
Non-electroconductive flux, connected structure, and method for producing connected structure
Provided is a non-electroconductive flux capable of enhancing productivity and impact resistance of a connected structure to be obtained and suppressing occurrence of solder flash. The non-electroconductive flux according to the present invention contains an epoxy compound, an acid anhydride curing agent, and an organophosphorus compound.
LAMINATED STRUCTURE, QUANTUM DEVICE, AND METHOD OF MANUFACTURING LAMINATED STRUCTURE
A laminated structure includes a cooling member; a circuit board provided on the cooling member and having a through hole; a device provided on the circuit board and including a quantum bit; and a bonding material configured to bond together the circuit board and the device. The bonding material includes a first bonding portion contacting a portion of an upper surface of the cooling member exposed from the through hole, an upper surface of the circuit board, and a lower surface of the device; and a second bonding portion provided around the first bonding portion in plan view and contacting the upper surface of the circuit board and the lower surface of the device. A thermal conductivity of the first bonding portion is higher than that of the second bonding portion. An elastic modulus of the second bonding portion is lower than that of the first bonding portion.