A device includes a photonic cryo die containing photonic components, and an electronic die bonded to the photonic die, the electronic die containing electrically conductive through substrate vias. The electrically conductive through silicon vias can electrically connect a backside redistribution layer to control circuitry for operation in a cryogenic environment in a compact package that exhibits low resistance and low parasitic capacitance.

A silicon wafer-scale system includes an optical interconnect layer between a processor layer and a memory layer. A single processor chip at the processor layer can access data of any memory chip at the memory layer by using an optical signal through an optoelectronic conversion module. Data exchange can be performed between processor chips at the processor layer by using an optical signal through an optoelectronic conversion module.