A micromechanical component for a sensor device including a substrate having a substrate surface, at least one stator electrode situated on the substrate surface and/or on the at least one intermediate layer covering at least partially the substrate surface, which is formed in each case from a first semiconductor and/or metal layer, at least one adjustably situated actuator electrode, which is formed in each case from a second semiconductor and/or metal layer, and a diaphragm spanning the at least one stator electrode and the at least one actuator electrode, including a diaphragm exterior side directed away from the at least one stator electrode, which is formed from a third semiconductor and/or metal layer, a stiffening and/or protective structure protruding at the diaphragm exterior side being formed from a fourth semiconductor and/or metal layer.

A method of manufacturing a semiconductor device includes providing a semiconductor layer having a first-type region and a second-type region that are stacked and interface with each other to form a p-n junction, the first-type region defining a first side of the semiconductor layer and the second-type region defining a second side of the semiconductor layer. The method further includes providing an insulating layer on the second side of the semiconductor layer and etching the semiconductor layer from the first side of the semiconductor layer toward the second side of the semiconductor layer to form a trench. The first-type region corresponds to one of a n-type region and a p-type region, and the second-type region corresponds to the other of the n-type region and the p-type region.

A device includes a substrate, a first electrode formed on the substrate and a structural layer formed on the substrate. The structural layer includes a movable mass and a fixed portion, the movable mass being suspended above the substrate and the first electrode being interposed between the substrate and the movable mass. A second electrode is spaced apart from an upper surface of the movable mass by a gap and an anchor couples the second electrode to the fixed portion of the structural layer. A method entails integrating formation of the second electrode into a wafer process flow in which the first electrode and the structural layer are formed.

A method includes bonding a first surface of a first semiconductor substrate to a first surface of a second semiconductor substrate and forming a cavity in the first area of the first semiconductor substrate, where forming the cavity comprises: supplying a passivation gas mixture that deposits a passivation layer on a bottom surface and sidewalls of the cavity, where during deposition of the passivation layer, a deposition rate of the passivation layer on the bottom surface of the cavity is the same as a deposition rate of the passivation layer on sidewalls of the cavity; and etching the first area of the first semiconductor substrate using an etching gas, where the etching gas is supplied concurrently with the passivation gas mixture, etching the first area of the first semiconductor substrate comprises etching in a vertical direction at a greater rate than etching in a lateral direction.

In an embodiment a device includes a substrate including an upper substrate surface and a lower substrate surface and a membrane-layer suspended above the upper substrate surface, wherein the substrate includes a recess penetrating the substrate between the lower substrate surface and the upper substrate surface, wherein the membrane-layer spans the recess, wherein the recess includes an upper recess region, an intermediate recess region, and a lower recess region, wherein the upper recess region is a part of the recess in direct vicinity to the upper substrate surface, the intermediate recess region is a part of the recess directly below the upper recess region, and the lower recess region is a part of the recess other than the upper recess region and the intermediate recess region, and wherein a cross-sectional area of the upper recess region determined parallel to the upper substrate surface is larger than a respective cross-sectional area of the intermediate recess region.

Various embodiments of the present disclosure are directed towards a microelectromechanical systems (MEMS) structure including a composite spring. A first substrate underlies a second substrate. A third substrate overlies the second substrate. The first, second, and third substrates at least partially define a cavity. The second substrate comprises a moveable mass in the cavity and between the first and third substrates. The composite spring extends from a peripheral region of the second substrate to the moveable mass. The composite spring is configured to suspend the moveable mass in the cavity. The composite spring includes a first spring layer comprising a first crystal orientation, and a second spring layer comprising a second crystal orientation different than the first crystal orientation.

A CMOS-based sensing device includes a substrate including an etched portion and a first region located on the substrate. The first region includes a membrane region formed over an area of the etched portion of the substrate, a flow sensor formed within the membrane region and a pressure sensor formed within the membrane region.

A silicon substrate having a first silicon substrate having a first surface with a cavity and a second surface opposite the first surface; a first silicon oxide film having a thickness dl on the first surface; a second silicon oxide film having a thickness d2 on a bottom of the cavity; and a third silicon oxide film having a thickness d3 on the second surface, where d1≤d3 and d1<d2, or d3<d1 and d2<d1.

A robust and general fabrication/manufacturing method is described herein for the fabrication of periodic three-dimensional (3D) hierarchical nanostructures in a highly scalable and tunable manner. This nanofabrication technique exploits the selected and repeated etching of spherical particles that serve as resist material and that can be shaped in parallel for each processing step. The method enables the fabrication of periodic, vertically aligned nanotubes at the wafer scale with nanometer-scale control in three dimensions including outer/inner diameters, heights/hole-depths, and pitches. The method was utilized to construct 3D periodic hierarchical hybrid silicon and hybrid nanostructures such as multi-level solid/hollow nanotowers where the height and diameter of each level of each structure can be configured precisely as well as 3D concentric plasmonic supported metal nanodisk/nanorings with tunable optical properties on a variety of substrates.

A method of forming a capacitive micromachined ultrasonic transducer (CMUT) device includes bonding a CMUT substrate to a silicon on insulator (SOI) substrate. The CMUT substrate has a first thickness and the SOI substrate includes a handle, a buried oxide layer, and a device layer. At least one of the CMUT substrate or the SOI substrate includes a patterned dielectric layer. The device layer is bonded to the patterned dielectric layer to form a plurality of sealed cavities and the device layer forms a diaphragm of the plurality of cavities. The method further includes reducing the first thickness of the CMUT substrate to a second thickness and forming a plurality of through-silicon vias from a second surface of the CMUT substrate opposite the first surface.