A device with an out-of-plane electrode includes a device layer positioned above a handle layer, a first electrode defined within the device layer, a cap layer having a first cap layer portion spaced apart from an upper surface of the device layer by a gap, and having an etch stop perimeter defining portion defining a lateral edge of the gap, and an out-of-plane electrode defined within the first cap layer portion by a spacer.

A device comprises a silicon-on-insulator (SOI) substrate having first and second silicon layers with an insulator layer interposed between them. A structural layer, having a first conductivity type, is formed on the first silicon layer. A well region, having a second conductivity type opposite from the first conductivity type, is formed in the structural layer, and resistors are diffused in the well region. A metallization structure is formed over the well region and the resistors. A first cavity extends through the metallization structure overlying the well region and a second cavity extends through the second silicon layer, with the second cavity stopping at one of the first silicon layer and the insulator layer. The well region interposed between the first and second cavities defines a diaphragm of a pressure sensor. An integrated circuit and the pressure sensor can be fabricated concurrently on the SOI substrate using a CMOS fabrication process.

A method and an apparatus for etching microstructures and the like that provides improved selectivity to surrounding materials when etching silicon using xenon difluoride (XeF2). Etch selectivity is greatly enhanced with the addition of hydrogen to the process chamber.

A method of manufacturing a plurality of through-holes (132) in a layer of material by subjecting the layer to directional dry etching to provide through-holes (132) in the layer of material; For batch-wise production, the method comprises after a step of providing a layer of first material (220) on base material and before the step of directional dry etching, providing a plurality of holes at the central locations of pits (210), etching base material at the central locations of the pits (210) so as to form a cavity (280) with an aperture (281), depositing a second layer of material (240) on the base material in the cavity (280), and subjecting the second layer of material (240) in the cavity (280) to said step of directional dry etching using the aperture (281) as the opening (141) of a shadow mask.

A method of manufacturing a plurality of through-holes in a layer of first material, for example for the manufacturing of a probe comprising a tip containing a channel. To manufacture the through-holes in a batch process, a layer of first material is deposited on a wafer comprising a plurality of pits a second layer is provided on the layer of first material, and the second layer is provided with a plurality of holes at central locations of the pits; using the second layer as a shadow mask when depositing a third layer at an angle, covering a part of the first material with said third material at the central locations, and etching the exposed parts of the first layer using the third layer as a protective layer.

Embodiments of the present disclosure describe a die with integrated microphone device using through-silicon vias (TSVs) and associated techniques and configurations. In one embodiment, an apparatus includes an apparatus comprising a semiconductor substrate having a first side and a second side disposed opposite to the first side, an interconnect layer formed on the first side of the semiconductor substrate, a through-silicon via (TSV) formed through the semiconductor substrate and configured to route electrical signals between the first side of the semiconductor substrate and the second side of the semiconductor substrate, and a microphone device formed on the second side of the semiconductor substrate and electrically coupled with the TSV. Other embodiments may be described and/or claimed.

A MEMS (microelectromechanical systems) structure comprises a MEMS wafer. A MEMS wafer includes a cap with cavities bonded to a structural layer through a dielectric layer disposed between the cap and the structural layer. Unique configurations of MEMS devices and methods of providing such are set forth which provide for, in part, creating rounded, scalloped or chamfered MEMS profiles by shaping the etch mask photoresist reflow, by using a multi-step deep reactive ion etch (DRIE) with different etch characteristics, or by etching after DRIE.

A method of forming an IC (integrated circuit) device is provided. The method includes receiving a first wafer including a first substrate and including a plasma-reflecting layer disposed on an upper surface thereof. The plasma-reflecting layer is configured to reflect a plasma therefrom. A dielectric protection layer is formed on a lower surface of a second wafer, wherein the second wafer includes a second substrate. The second wafer is bonded to the first wafer, such that a cavity is formed between the plasma-reflecting layer and the dielectric protection layer. An etch process is performed with the plasma to form an opening extending from an upper surface of the second wafer and through the dielectric protection layer into the cavity. A resulting structure of the above method is also provided.

Various embodiments of the present disclosure are directed towards a microelectromechanical systems (MEMS) structure including a composite spring. A first substrate underlies a second substrate. A third substrate overlies the second substrate. The first, second, and third substrates at least partially define a cavity. The second substrate comprises a moveable mass in the cavity and between the first and third substrates. The composite spring extends from a peripheral region of the second substrate to the moveable mass. The composite spring is configured to suspend the moveable mass in the cavity. The composite spring includes a first spring layer comprising a first crystal orientation, and a second spring layer comprising a second crystal orientation different than the first crystal orientation.

MEMS devices and methods for forming the same are provided. A first metal interconnect structure is formed on a first semiconductor substrate to connect to a CMOS control circuit in the first semiconductor substrate. A bonding layer having a cavity is formed on the first metal interconnect structure, and then bonded with a second semiconductor substrate. A conductive plug passes through a first region of the second semiconductor substrate, through the bonding layer, and on the first metal interconnect structure. A second metal interconnect structure includes a first end formed on the first region of the second semiconductor substrate, and a second end connected to the conductive plug. Through-holes are disposed through a second region of the second semiconductor substrate and through a top portion of the bonded layer that is on the cavity to leave a movable electrode to form the MEMS device.