B81C2201/0133

ENGINEERED SUBSTRATES, FREE-STANDING SEMICONDUCTOR MICROSTRUCTURES, AND RELATED SYSTEMS AND METHODS
20220396476 · 2022-12-15 ·

A free-standing microstructure may be formed from an engineered substrate including a first silicon layer, a second silicon layer, and an intermediate layer. The second silicon layer may include a monocrystalline silicon film. The intermediate layer may be between the first silicon layer and the second silicon layer. The intermediate layer may include a silicon- or germanium-based material having a different lattice constant than the first silicon layer or the second silicon layer. The intermediate layer of the free-standing microstructure may further include one or more voids wherein at least a portion of the silicon- or germanium-based material is absent between the first silicon layer and the second silicon layer.

Method for manufacturing micromechanical structures in a device wafer
11524893 · 2022-12-13 · ·

The disclosure relates to a method for manufacturing recessed micromechanical structures in a MEMS device wafer. First vertical trenches in the device wafer define the horizontal dimensions of both level and recessed structures. The horizontal face of the device wafer and the vertical sidewalls of the first vertical trenches are then covered with a self-supporting etching mask which is made of a self-supporting mask material, which is sufficiently rigid to remain standing vertically in the location where it was deposited even as the sidewall upon which it was deposited is etched away. Recess trenches are then etched under the protection of the self-supporting mask. The method allows a spike-preventing aggressive etch to be used for forming the recess trenches, without harming the sidewalls in the first vertical trenches.

Method of texturing semiconductor substrate, semiconductor substrate manufactured using the method, and solar cell including the semiconductor substrate

An embodiment includes a method of texturing a semiconductor substrate, a semiconductor substrate manufactured using the method, and a solar cell including the semiconductor substrate, the method including: forming metal nanoparticles on a semiconductor substrate, primarily etching the semiconductor substrate, removing the metal nanoparticles, and secondarily etching the primarily etched semiconductor substrate to form nanostructures.

MEMS MICROPHONE AND PREPARATION METHOD THEREFOR
20220386052 · 2022-12-01 ·

A preparation method for a micro-electromechanical systems (MEMS) microphone includes the steps of: providing a silicon substrate having a silicon surface; forming an enclosed cavity in the silicon substrate; forming a plurality of spaced apart acoustic holes in the silicon substrate, each acoustic hole having two openings, one of which communicating with the cavity and the other one located on the silicon surface; forming a sacrificial layer on the silicon substrate, which includes a first filling portion, a second filling portion and a shielding portion; forming a polysilicon layer on the shielding portion; forming a recess in the silicon substrate on the side away from the silicon surface; and removing the first filling portion, the second filling portion and part of the shielding portion so that the recess is brought into communication with the cavity to form a back chamber, and that the polysilicon layer, the remainder of the shielding portion and the silicon substrate together delimit a hollow chamber, the hollow chamber communicating with the opening of the plurality of acoustic holes away from the cavity, completing the MEMS microphone.

Method for manufacturing a microelectronic device comprising a membrane suspended above a cavity

A method for manufacturing a microelectronic device with a membrane suspended above at least one final cavity, may involve providing a supporting substrate having at least one elementary cavity, and a donor substrate. The method may include assembling the supporting and donor substrate, then thinning the donor substrate so as to form the membrane. Advantageously, the method may include forming at least one membrane anchoring pillar. After the forming of the at least one anchoring pillar, and after the assembling, the method may include etching the surface layer of the supporting substrate so as to widen the at least one elementary cavity, to form the final cavity, the etching being configured to selectively etch the surface layer with respect to the anchoring pillar.

MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) VIBRATION SENSOR AND FABRICATING METHOD THEREOF
20220371881 · 2022-11-24 ·

A MEM vibration sensor includes a substrate including a first supporting-portion and a cavity and a sensing-device disposed on the substrate. The sensing-device includes a second supporting-portion correspondingly disposed over and connected with the first supporting-portion, a first sensing-unit disposed on the cavity, a first mass-block disposed on the cavity, a second sensing-unit disposed on the first sensing-unit and the first mass-block, a first metal pad disposed on the third supporting-portion and electrically coupled with the first sensing-unit, and a second metal pad disposed on the third supporting-portion and electrically coupled with the second sensing-unit.

Method for manufacturing a plurality of resonators

A method of manufacturing a plurality of resonators, each formed by a membrane sealing a cavity, includes forming a plurality of cavities starting from one face called the front face of a support substrate, the plurality of cavities comprising central cavities and peripheral cavities arranged around the assembly formed by the central cavities, and forming central membranes and peripheral membranes covering the central cavities and peripheral cavities, respectively, by the transfer of a coverage film on the front face of the support substrate. At least part of the peripheral membranes is removed.

Method for manufacturing three-dimensionally structured member, method for manufacturing acceleration pickup, acceleration pickup, and acceleration sensor

The purpose of the present invention is to provide a method for manufacturing a three-dimensionally structured member which can be made by a simpler process. The method for manufacturing a three-dimensionally structured member includes shaping a flat plate-shaped base member to produce a three-dimensionally structured member having a plurality of sections that are different from one another in thickness. The manufacturing method comprises: a mask formation step for forming a mask over the whole of at least one main surface of the base member; a mask removal step for removing a part of the mask; and an etching step for etching an exposed part of the base member wherein a combination of the mask removal step and the etching step is performed on the mask and the base member that correspond to each of the plurality of sections of the three-dimensionally structured member, in the order from thinnest to the thickest of thicknesses of the three-dimensionally structured members.

Piezoelectric micromachined ultrasonic transducer and method of fabricating the same

A piezoelectric micromachined ultrasonic transducer (PMUT) includes a substrate, a stopper, and a membrane, where the substrate and the stopper are composed of same single-crystalline material. The substrate has a cavity penetrating the substrate, and the stopper protrudes from a top surface of the substrate and surrounds the edge of the cavity. The membrane is disposed over the cavity and attached to the stopper.

SILICON NANOWIRE CHIP AND SILICON NANOWIRE CHIP-BASED MASS SPECTRUM DETECTION METHOD
20220359180 · 2022-11-10 ·

The present disclosure discloses a silicon nanowire chip and silicon nanowire chip-based mass spectrometry detection method. The detection method includes the following steps: step 1 of manufacturing a silicon nanowire chip, comprising: subjecting a monocrystalline silicon wafer to a surface washing pretreatment, a metal-assisted etching and a post-alkali etching to obtain a silicon nanowire chip with a tip, and performing a surface chemical modification or a nanomaterial modification on the silicon nanowire chip; step 2 of evaluating mass spectrometry performance of the silicon nanowire chip; and step 3 of performing a tip-contact sampling and in-situ ionization mass spectrometry detection.