A configuration for a capacitive pressure sensor uses a silicon on insulator wafer to create an electrically isolated sensing node across a gap from a pressure sensing wafer. The electrical isolation, small area of the gap, and silicon material throughout the capacitive pressure sensor allow for minimal parasitic capacitance and avoid problems associated with thermal mismatch.

A microelectromechanical system, including a substrate having a major plane of extension. The microelectromechanical system includes a mass structure. The mass structure is formed to be movable relative to the substrate in a vertical direction, perpendicularly to the major plane of extension. The mass structure includes an electrode structure. The substrate includes a counter-electrode structure. The electrode structure and the counter-electrode structure are coupled capacitively. The mass structure has a deformation in a resting state of the microelectromechanical system. The electrode structure and/or the counter-electrode structure are formed as a function of the deformation of the mass structure.

A PMUT includes a substrate, a stopper, and a multi-layered structure, where the substrate includes a corner, and a cavity is disposed in the substrate. The stopper is in contact with the corner of the substrate and the cavity. The multi-layered structure is disposed over the cavity and attached to the stopper and the multi-layered structure includes at least one through hole in contact with the cavity.

A method for producing a microelectromechanical sensor. The microelectromechanical sensor is produced by connecting a cap wafer to a sensor wafer. The cap wafer has a bonding structure for connecting the cap wafer to the sensor wafer. The sensor wafer has a sensor core having a movable structure. The cap wafer has a stop structure for limiting an excursion of the movable structure. The method includes a first step and a second step following the first step, the stop surface of the stop structure being situated at the level of the original surface of the unprocessed cap wafer.

The invention relates to a silicon-based component with at least one reduced contact surface which, formed from a method combining at least one oblique side wall etching step with a “Bosch” etch of vertical side walls, improves, in particular, the tribology of components formed by micromachining a silicon-based wafer.

A method for processing a silicon substrate includes forming a structure having a bottom surface and a depth of 200 μm or more or 300 μm or more from a first surface of a silicon substrate, forming a protective film on an inner wall of the structure, and performing plasma etching so as to selectively remove the protective film disposed on the bottom surface of the structure with respect to the protective film disposed on the substantially perpendicular side wall of the structure, wherein the plasma etching is performed under the condition in which plasma with a sheath length at least 10 times the depth when the depth is 200 μm or more, or at least 5 time the depth when the depth is 300 μm or more, is generated and a mean free path of ions generated in the plasma is longer than the sheath length.

A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.

A method for manufacturing a protective layer for protecting an intermediate structural layer against etching with hydrofluoric acid, the intermediate structural layer being made of a material that can be etched or damaged by hydrofluoric acid, the method comprising the steps of: forming a first layer of aluminum oxide, by atomic layer deposition, on the intermediate structural layer; performing a thermal crystallization process on the first layer of aluminum oxide, forming a first intermediate protective layer; forming a second layer of aluminum oxide, by atomic layer deposition, above the first intermediate protective layer; and performing a thermal crystallization process on the second layer of aluminum oxide, forming a second intermediate protective layer and thereby completing the formation of the protective layer. The method for forming the protective layer can be used, for example, during the manufacturing steps of an inertial sensor such as a gyroscope or an accelerometer.

A symmetrical MEMS accelerometer. The accelerometer includes a top half and a bottom half bonded together to form the frame and the mass located within the frame. The frame and the mass are connected through resilient beams. A plurality of hollowed parts and the first connecting parts are formed on the top and bottom side of the mass, respectively. The second connecting parts are formed on the top and bottom side of the frame, respectively. The resilient beams connect the first connecting part with the second connecting part. Several groups of comb structures are formed on top of the hollowed parts. Each comb structure includes a plurality of moveable teeth and fixed teeth. The moveable teeth extend from the first connecting part and the fixed teeth extend from the second connecting part. Capacitance is formed between the movable teeth and the fixed teeth. Since the accelerometer is symmetrical with a large mass, it has a large capacitance with a low damping force.

Various embodiments may provide a method of fabricating a meta-lens structure. The method may include forming a first dielectric layer in contact with a silicon wafer. The method may also include forming a second dielectric layer in contact with the first dielectric layer. A refractive index of the second dielectric layer may be different from a refractive index of the first dielectric layer. The method may further include, in patterning the second dielectric layer. The method may additionally include removing at least a portion of the silicon wafer to expose the first dielectric layer.