Patent classifications
B41J2/04511
SEMICONDUCTOR APPARATUS, LIQUID DISCHARGE HEAD SUBSTRATE, LIQUID DISCHARGE HEAD, AND LIQUID DISCHARGE APPARATUS
An apparatus includes a substrate, a transistor provided on the substrate and connected to a first terminal supplied with a first voltage, an anti-fuse element provided on the substrate and connected between the transistor and a second terminal supplied with a second voltage, a first resistive element provided on the substrate and connected in parallel to the anti-fuse element and between the transistor and the second terminal, and an adjusting unit provided on the substrate and configured to function so as to reduce an influence of variation in resistance of the first resistive element in reading out of information from the anti-fuse element.
Semiconductor device and liquid discharge head substrate
A semiconductor device is provided. The device comprises: a first transistor that includes a first primary terminal, a second primary terminal and a first control terminal; a second transistor that includes a third primary terminal, a fourth primary terminal and a second control terminal; and a resistive element. The first and third primary terminal are connected to a first voltage line. The second primary terminal and one terminal of the resistive element are connected to a second voltage line. The first and second control terminal, the fourth primary terminal and the other terminal of the resistive element are connected to a node. A potential change in the third primary terminal is transmitted to the first control terminal by capacitive coupling between the third primary terminal and the node, turning on the first transistor.
Semiconductor device and recording device
A semiconductor device includes, an anti-fuse element, a transistor connected via the anti-fuse element to a power source terminal which may apply a voltage to the anti-fuse element, an ESD protection element connected to the power source terminal via a node, and a first resistive element disposed in an electric path between the node and the anti-fuse element, wherein resistance of the first resistive element increases with an increase of a voltage applied to the first resistive element.
SEMICONDUCTOR DEVICE AND RECORDING DEVICE
A semiconductor device includes, an anti-fuse element, a transistor connected via the anti-fuse element to a power source terminal which may apply a voltage to the anti-fuse element, an ESD protection element connected to the power source terminal via a node, and a first resistive element disposed in an electric path between the node and the anti-fuse element, wherein resistance of the first resistive element increases with an increase of a voltage applied to the first resistive element.
ELECTRIC CIRCUIT BOARD AND LIQUID EJECTION HEAD
An electric circuit board includes: a booster circuit configured to generate a pump drive signal by boosting a pump reference signal having a reference voltage based on a booster circuit drive signal; a first wiring for transmitting the pump drive signal; a second wiring for transmitting the pump reference signal; a third wiring for transmitting the booster circuit drive signal; and a plurality of fourth wirings for transmitting signals related to an ejection element configured to eject a liquid, wherein the second wiring and the third wiring each have a portion disposed at a position spaced apart from the first wiring by a distance shorter than a protection distance, and have a short circuit protection circuit connected thereto, and the plurality of fourth wirings include one or more first type wirings disposed at a position spaced apart from the first wiring by a distance longer than the protection distance.
Semiconductor device, liquid discharge head, and liquid discharge apparatus
A device, comprising a plurality of units arrayed in a predetermined direction, a first terminal configured to supply a voltage to the plurality of units, and a second terminal configured to supply a voltage to the plurality of units, wherein the plurality of units include a first unit including a memory element arranged between the first terminal and the second terminal, and a first transistor configured to perform write to the memory element, and a second unit including a second transistor arranged between the first terminal and the second terminal in correspondence with the first transistor of the first unit.