A drop ejector array device includes a first plurality and a second plurality of drop ejectors that are alternatingly disposed along an array direction on the substrate surface. A voltage input terminal and a current return terminal are disposed on the substrate surface. A first power bus line connects the first plurality to the voltage input terminal. A second power bus line connects the second plurality to the voltage input terminal. The second power bus line is electrically connected to the first power bus line by a primary power bus connector line. A first current return bus line connects the first plurality to the current return terminal. A second current return bus line connects the second plurality to the current return terminal. The second current return bus line is electrically connected to the first current return bus line by a primary current return bus connector line.

A liquid jet head and so on capable of reducing both of a manufacturing cost and power consumption are provided. The liquid jet head according to an embodiment of the present disclosure is provided with a jet section and at least one drive board. The drive board is provided with a first input terminal and a second input terminal, a plurality of drive devices, a plurality of transmission lines, and a plurality of terminal resistors. The drive devices each have a first input/output section and a second input/output section. The plurality of drive devices include a first drive device and a second drive device. The plurality of transmission lines include a first transmission line, a second transmission line, and at least one third transmission line. The plurality of termination resistors include a first termination resistor, a second termination resistor, and a third termination resistor.

A drive circuit includes a first voltage output circuit coupled to a first terminal and outputting a first voltage signal, a second voltage output circuit coupled to a second terminal and outputting a second voltage signal, and a drive signal output circuit coupled to the first terminal and outputting a drive signal. In a first mode, the second voltage output circuit outputs the second voltage signal and the drive signal output circuit outputs the drive signal whose voltage value varies. In a second mode, the second voltage output circuit outputs the second voltage signal and the drive signal output circuit outputs the drive signal which is constant at a third voltage value. In a third mode, the first voltage output circuit outputs the first voltage signal and the second voltage output circuit outputs the second voltage signal.

In some examples, a circuit includes a data line, an input line, a first memory element, and a decoder to receive an address and to enable the first memory element for access in response to the address. The selector is responsive to the data line to select the first memory element, where the selector is to select the first memory element responsive to the data line having a first value, and where the data line is to communicate data of a second memory element in response to the second memory element being enabled for access. The input line is to communicate data of the first memory element in response to the first memory element being selected by the selector.

A fluidic die includes a number of actuators to eject fluid from the fluidic die. The number of actuators form a number of primitives. The fluidic die includes a plurality of delays within a column of the primitives, and a processing device to control the delays through which a number of activation pulses pass. The activation pulses activate each of the actuators associated with the primitives. The activation pulses are delayed between the primitives via at least one of the delays to reduce peak power demands of the fluidic die.

A fluidic die may include a substrate supporting a fluid actuator address line and first and second groups of fluid actuators connected to the fluid actuator address line. The first group of fluid actuators may include first and second types of fluid actuators having different operating characteristics. The second group of fluid actuators may include the first and the second types of fluid actuators. The fluid actuators of the first and second groups have addresses such that a fluid actuator of the first type in the first group and a fluid actuator of the second type in the second group are both enabled in response to a single enabling event on the fluid actuator address line.

In some examples, a fluidic die includes a set of fluid actuators arranged in an order, and a controller to determine, based on input control information relating to controlling actuation of the plurality of fluid actuators, whether a first fluid actuator of the plurality of fluid actuators is to be actuated and whether a second fluid actuator within a specified proximity of the first fluid actuator in the order is to be actuated, and in response to determining that the first fluid actuator is to be actuated and the second fluid actuator within the specified proximity of the first fluid actuator in the order is not to be actuated, activate a delay element associated with the first fluid actuator, the delay element to delay an activation signal propagated to selected fluid actuators of the set of fluid actuators in response to an actuation event.

An integrated circuit to drive a plurality of fluid actuators is disclosed. The integrated circuit analog delay circuits coupled in series and to a fire input to receive a fire signal in succession. Each analog delay circuit receives the fire signal and, after a delay, provides the fire signal via an output to a corresponding fluid actuator. A bias circuit is coupled to each of the of analog delay circuits. The bias circuit provides a bias signal to control the delay.

A driving circuit generating a driving signal, includes a modulator generating a modulated signal by performing pulse modulation on a signal specifying a waveform of the driving signal, an amplifier generating an amplified signal by amplifying the modulated signal, and a smoothing section generating the driving signal by smoothing the amplified signal. The amplifier includes first and second transistors coupled in series between a voltage line to which a voltage which is higher than a ground voltage is supplied and a grounding conductor to which the ground voltage is supplied, and a third transistor having a drain electrode coupled to a gate electrode of the second transistor and a source electrode coupled to the grounding conductor. The first and second transistors are exclusively set to an On state in accordance with the modulated signal, and the amplified signal is output from a node which couples the first and second transistors.

In the technology of the present disclosure, multiple nozzles included in a printing head are stably driven while disparity in the usage frequency of each nozzle is suppressed. The dot counter scans the digital halftone data in the X direction and performs accumulation-counting on the pixel value Ixy (the number of printing dots) of each pixel for each address y with the accumulation counter CntCum(y). The signal value Gxy of the corresponding pixel address (x, y) is obtained from the division pattern memory unit. The nozzle selection unit selects the nozzle to be used for forming a printing dot, based on the counted values of the accumulation counter CntCum and the signal value Gxy of the division pattern. Then, the address n of the nozzle memory corresponding to the selected nozzle to form a printing dot is determined.