A driving circuit includes an amplification circuit that outputs an amplified modulation signal and a level shift circuit. In the level shift circuit, when a reference potential of the amplified modulation signal is shifted to a second potential from a first potential, a second gate driver outputs a third gate signal for controlling a third transistor to be nonconductive and a fourth gate signal for controlling a fourth transistor to be conductive, then outputs the third gate signal for controlling the third transistor to be conductive and the fourth gate signal for controlling the fourth transistor to be nonconductive, and thereafter outputs the third gate signal for controlling the third transistor to be nonconductive and the fourth gate signal for controlling the fourth transistor to be conductive.

The interface region may include a region in which first intensity is higher than second intensity and in which the first intensity is higher than third intensity, where a degree of orientation of the (−211) crystal face of the second layer is denoted as the first intensity, the degree of orientation of the (−111) crystal face of the second layer is denoted as the second intensity, and the degree of orientation of the (002) crystal face of the second layer is denoted as the third intensity. The surface-layer region may include a region in which the first intensity is higher than the third intensity and in which the second intensity is higher than the third intensity.

In some examples, a circuit includes a data line, an input line, a first memory element, and a decoder to receive an address and to enable the first memory element for access in response to the address. The selector is responsive to the data line to select the first memory element, where the selector is to select the first memory element responsive to the data line having a first value, and where the data line is to communicate data of a second memory element in response to the second memory element being enabled for access. The input line is to communicate data of the first memory element in response to the first memory element being selected by the selector.

In one example in accordance with the present disclosure, a fluidic die is described. The fluidic die includes an array of firing subassemblies grouped into zones. Each firing subassembly includes 1) a firing chamber, 2) a fluid actuator, and 3) a sensor plate. The fluidic die also includes a measurement device per zone to measure a voltage indicative of an impedance within a selected firing chamber. The fluidic die includes a selector per firing subassembly to couple a selected sensor plate to the measurement device. A selector is adjacent a respective firing subassembly and a distance between the selector and the measurement device is different as compared to other selectors.

Fluid ejection devices with multiple activation modes are disclosed. An example printhead assembly includes a fluid ejection nozzle, a first resistor fluidically coupled to the fluid ejection nozzle, and a second resistor fluidically coupled to the fluid ejection nozzle. The example printhead also includes an addressing circuit to receive a nozzle address and an activation mode to activate the fluid ejection nozzle. The activation mode determines which of the first resistor and the second resistor are to be energized.

Examples include a fluid ejection die. Examples comprise a set of nozzles, where each respective nozzle includes a respective fluid ejector. Examples further include respective identification logic for each nozzle, where the respective identification logic is connected to the respective nozzle and fluid ejector thereof. Furthermore, the identification logic for each nozzle of the set has a component characteristic that is different from other identification logic for nozzles of the set. Accordingly, each identification logic is to output a different actuation signal responsive to actuation of the fluid ejector.

In some examples, a circuit for use with a fluid ejection device includes a plurality of decoders responsive to a common address to activate respective control signals at different times for selecting respective memories of the fluid ejection device. Each respective decoder of the plurality of decoders comprising a discharge switch to deactivate a control signal of the respective decoder while another decoder of the plurality of decoders is activating a control signal in response to the common address.

An integrated circuit to drive a plurality of fluid actuation devices includes an ID line, a fire line, a discharge path, a memory element, and a latch. The memory element is electrically coupled to the fire line and the discharge path. The latch disables the discharge path in response to a first logic level on the ID line and enables the discharge path in response to a second logic level on the ID line.

Examples include a fluidic die. The fluidic die comprises an array of field effect transistors including field effect transistors of a first size and field effect transistors of a second size. At least one connecting member interconnects at least some of the field effect transistors of the array of field effect transistors. The fluidic die further comprises a first fluid actuator connected to a first set of field effect transistors having at least one field effect transistor of the first size. The die includes a second fluid actuator connected to a second respective set of field effect transistors having a first respective field effect transistor of the second size interconnected to at least one other field effect transistor of the array.

A liquid discharge head includes a plurality of discharge elements, a plurality of driving elements, a plurality of control circuits, a first ground wiring and a first power supply wiring configured to supply power to the plurality of discharge elements and the plurality of driving elements, and a second ground wiring and a second power supply wiring configured to supply power to the plurality of control circuits. The first ground wiring and the first power supply wiring include, in a first conductive layer of a plurality of conductive layers, a first wiring group extending in a first direction, and in a second conductive layer, a second wiring group extending in a second direction which intersects with the first direction. The second power supply wiring is arranged on one of the first conductive layer and the second conductive layer.