A patterned backside stress compensation film having different stress in different sectors is formed on a backside of a substrate to reduce combination warpage of the substrate. The film can be formed by employing a radio frequency electrode assembly including plurality of conductive plates that are biased with different RF power and cause local variations in the plasma employed to deposit the backside film. Alternatively, the film may be deposited with uniform stress, and some of its sectors are irradiated with ultraviolet radiation to change the stress of these irradiated sectors. Yet alternatively, multiple backside deposition processes may be sequentially employed to deposit different backside films to provide a composite backside film having different stresses in different sectors.

A patterned backside stress compensation film having different stress in different sectors is formed on a backside of a substrate to reduce combination warpage of the substrate. The film can be formed by employing a radio frequency electrode assembly including plurality of conductive plates that are biased with different RF power and cause local variations in the plasma employed to deposit the backside film. Alternatively, the film may be deposited with uniform stress, and some of its sectors are irradiated with ultraviolet radiation to change the stress of these irradiated sectors. Yet alternatively, multiple backside deposition processes may be sequentially employed to deposit different backside films to provide a composite backside film having different stresses in different sectors.

A method for forming a coating on a component of a substrate processing system includes arranging the component in a processing chamber and applying a ceramic material to form the coating on one or more surfaces of the component. The ceramic material is comprised of a mixture including a rare earth oxide and having a grain size of less than 150 nm and is applied while a temperature within the processing chamber is less than 400° C. The coating has a thickness of less than 30 μm. A heat treatment process is performed on the coated component in a heat treatment chamber. The heat treatment process includes increasing a temperature of the heat treatment chamber from a first temperature to a second temperature that does not exceed a melting temperature of the mixture over a first period and maintaining the second temperature for a second period.

A method for forming a coating on a component of a substrate processing system includes arranging the component in a processing chamber and applying a ceramic material to form the coating on one or more surfaces of the component. The ceramic material is comprised of a mixture including a rare earth oxide and having a grain size of less than 150 nm and is applied while a temperature within the processing chamber is less than 400° C. The coating has a thickness of less than 30 μm. A heat treatment process is performed on the coated component in a heat treatment chamber. The heat treatment process includes increasing a temperature of the heat treatment chamber from a first temperature to a second temperature that does not exceed a melting temperature of the mixture over a first period and maintaining the second temperature for a second period.

Methods of selectively depositing blocking layers on conductive surfaces over dielectric surfaces are described. In some embodiments, a 4-8 membered substituted heterocycle is exposed to a substrate to selectively form a blocking layer. In some embodiments, a layer is selectively deposited on the dielectric surface after the blocking layer is formed. In some embodiments, the blocking layer is removed.

Methods of selectively depositing blocking layers on conductive surfaces over dielectric surfaces are described. In some embodiments, a 4-8 membered substituted heterocycle is exposed to a substrate to selectively form a blocking layer. In some embodiments, a layer is selectively deposited on the dielectric surface after the blocking layer is formed. In some embodiments, the blocking layer is removed.

A method for manufacturing a group III nitride substrate is described. The method involves forming group III nitride films having a group III element face on a surface thereof, on both surfaces of a substrate, so as to produce a group III nitride film carrier. The group III nitride film carrier is subjected to ion implantation and adhered to a base substrate containing polycrystals containing a group III nitride as a major component. The group III nitride film carrier is spaced from the base substrate to transfer the ion-implanted region to the base substrate, so as to form a group III nitride film having an N face on a surface thereof on the base substrate. A group III nitride film is formed on the group III nitride by a THVPE method, so as to produce a thick film of a group III nitride film.

This disclosure relates to a method (100) for passivating a semiconductor structure, comprising a semiconductor layer and an oxide layer on the semiconductor layer; a semiconductor structure; and a vacuum processing system. The method (100) comprises providing the semiconductor structure (110) in a vacuum chamber (310) and, while keeping the semiconductor structure in the vacuum chamber (120) throughout a refinement period with a duration of at least 25 s refining the oxide layer (130) by maintaining temperature (131) of the semiconductor structure within a refinement temperature range extending from 20° C., to 800° C., and maintaining total pressure (132) in the vacuum chamber below a maximum total pressure, of 1×10.sup.−3 mbar.

This disclosure relates to a method (100) for passivating a semiconductor structure, comprising a semiconductor layer and an oxide layer on the semiconductor layer; a semiconductor structure; and a vacuum processing system. The method (100) comprises providing the semiconductor structure (110) in a vacuum chamber (310) and, while keeping the semiconductor structure in the vacuum chamber (120) throughout a refinement period with a duration of at least 25 s refining the oxide layer (130) by maintaining temperature (131) of the semiconductor structure within a refinement temperature range extending from 20° C., to 800° C., and maintaining total pressure (132) in the vacuum chamber below a maximum total pressure, of 1×10.sup.−3 mbar.

A method of forming graphene layers is disclosed. The method includes precleaning the substrate with a plasma formed from an argon- and hydrogen-containing gas, followed by forming a graphene layer by exposing the substrate to a microwave plasma to form a graphene layer on the substrate. The microwave plasma comprises hydrocarbon and hydrogen radicals. The substrate is then cooled. A capping layer may also be formed.