C23F1/44

SEMICONDUCTOR DEVICE WITH REDUCED VIA RESISTANCE
20200090993 · 2020-03-19 ·

A semiconductor interconnect structure that has a first portion included in an upper interconnect level and a second portion included in a lower interconnect level. The semiconductor interconnect structure has a segment of dielectric capping material that is in contact with the bottom of the first portion, which separates, in part, the upper interconnect level from a lower interconnect level. The second portion is in electrical contact with the first portion.

SEMICONDUCTOR DEVICE WITH REDUCED VIA RESISTANCE
20200090994 · 2020-03-19 ·

A semiconductor interconnect structure having a first electrically conductive structure having a plurality of bottom portions; a dielectric capping layer, at least a portion of the dielectric capping layer being in contact with a first bottom portion of the plurality of bottom portions; and a second electrically conductive structure in electrical contact with a second bottom portion of the plurality of bottom portions. A method of forming the interconnect structure is also provided.

SEMICONDUCTOR DEVICE WITH REDUCED VIA RESISTANCE
20200090994 · 2020-03-19 ·

A semiconductor interconnect structure having a first electrically conductive structure having a plurality of bottom portions; a dielectric capping layer, at least a portion of the dielectric capping layer being in contact with a first bottom portion of the plurality of bottom portions; and a second electrically conductive structure in electrical contact with a second bottom portion of the plurality of bottom portions. A method of forming the interconnect structure is also provided.

ETCHING COMPOSITIONS
20200079998 · 2020-03-12 ·

The present disclosure is directed to etching compositions that are useful, e.g., for selectively removing tungsten (W) and/or titanium nitride (TiN) from a semiconductor substrate as an intermediate step in a multistep semiconductor manufacturing process.

Copper etchant composition
10577696 · 2020-03-03 · ·

Provided is a copper etchant composition including: a first organic acid containing one or more amine groups, and one or more carboxylic acid groups; a second organic acid; an amine compound; hydrogen peroxide; and a phosphate compound, which has the increased number of processing sheets and etching uniformity, when etching copper.

Copper etchant composition
10577696 · 2020-03-03 · ·

Provided is a copper etchant composition including: a first organic acid containing one or more amine groups, and one or more carboxylic acid groups; a second organic acid; an amine compound; hydrogen peroxide; and a phosphate compound, which has the increased number of processing sheets and etching uniformity, when etching copper.

METHOD FOR MANUFACTURING TRANSFER FILM INCLUDING SEED LAYER, METHOD FOR MANUFACTURING CIRCUIT BOARD BY SELECTIVELY ETCHING SEED LAYER, AND ETCHING SOLUTION COMPOSITE

The disclosure relates to a method for manufacturing a transfer film including an electrode layer, the method comprising: an electrode layer formation step of forming an electrode layer on a carrier member by using a conductive material; a placement step of placing the carrier member on at least one side of an insulating resin layer respectively; a bonding step of bonding the carrier member and the insulating resin layer together by applying pressure thereto; and a transfer step of removing the carrier member to transfer the electrode layer on the insulating resin layer.

Semiconductor device with reduced via resistance

A method of fabricating a semiconductor interconnect structure by providing a semiconductor structure with a dielectric layer with and an embedded electrically conductive structure. A dielectric capping layer and a metal capping layer separating a second dielectric layer located above the first dielectric layer. The segment of metal capping layer covers at least a portion of a top surface of the first electrically conductive structure. Exposing parts of both the first electrically conductive structure and the dielectric capping layer by forming an opening in the second dielectric layer and the metal capping layer. Forming a second electrically conductive structure in the opening, such that (i) the second electrically conductive structure is located over part of the dielectric capping layer, and (ii) the second electrically conductive structure is in electrical contact with the first electrically conductive structure.

Semiconductor device with reduced via resistance

A method of fabricating a semiconductor interconnect structure by providing a semiconductor structure with a dielectric layer with and an embedded electrically conductive structure. A dielectric capping layer and a metal capping layer separating a second dielectric layer located above the first dielectric layer. The segment of metal capping layer covers at least a portion of a top surface of the first electrically conductive structure. Exposing parts of both the first electrically conductive structure and the dielectric capping layer by forming an opening in the second dielectric layer and the metal capping layer. Forming a second electrically conductive structure in the opening, such that (i) the second electrically conductive structure is located over part of the dielectric capping layer, and (ii) the second electrically conductive structure is in electrical contact with the first electrically conductive structure.

CONNECTION TERMINAL AND METHOD FOR PRODUCING CONNECTION TERMINAL

A connection terminal in which alloy particles made of an intermetallic compound containing tin and palladium are exposed on an outermost surface of a contact configured to electrically contact a mating conductor and distributed on a surface of a base material at least in the contact, wherein: a tin part made of pure tin or an alloy having a higher ratio of tin to palladium than the intermetallic compound is not exposed on a plane passing through a point where a height of the alloy particles from the surface of the base material is highest.