Nanotwinned copper and non-nanotwinned copper may be electroplated to form mixed crystal structures such as 2-in-1 copper via and RDL structures or 2-in-1 copper via and pillar structures. Nanotwinned copper may be electroplated on a non-nanotwinned copper layer by pretreating a surface of the non-nanotwinned copper layer with an oxidizing agent or other chemical reagent. Alternatively, nanotwinned copper may be electroplated to partially fill a recess in a dielectric layer, and non-nanotwinned copper may be electroplated over the nanotwinned copper to fill the recess. Copper overburden may be subsequently removed.

Provided are cleaning methods and systems to remove unintended metallic deposits from electroplating apparatuses using reverse current deplating techniques. Such cleaning involves positioning a cleaning (deplating) disk in an electroplating cup similar to a regular processed substrate. The front surface of the cleaning disk includes a corrosion resistant conductive material to form electrical connections to deposits on the cup's surfaces. The disk is sealed in the cup and submerged into a plating solution. A reverse current is then applied to the front conductive surface of the disk to initiate deplating of the deposits. Sealing compression in the cup may change during cleaning to cause different deformation of the lip seal and to form new electrical connections to the deposits. The proposed cleaning may be applied to remove deposits formed during electroplating of alloys, in particular, tin-silver alloys widely used for semiconductor and wafer level packaging.

An electrolytic processing jig configured to perform an electrolytic processing on a processing target substrate includes a base body having a flat plate shape; an electrode provided at the base body; three or more terminals provided at the base body, each having elasticity and configured to be brought into contact with a peripheral portion of the processing target substrate; and a detecting unit configured to electrically detect a contact of at least one of the terminals with the processing target substrate.

A plating method for plating a substrate by increasing a current value from a predetermined current value to a first current value is provided. The plating method plates the substrate for a first predetermined period with the first current value when a first current density corresponding to the first current value is lower than a limiting current density. This plating method includes measuring a voltage value applied to the substrate, and when the current value is increased from the predetermined current value to the first current value, determining whether the first current density is equal to or more than the limiting current density or not based on an amount of change in the voltage value.

There is provided a substrate holder configured to hold a substrate, the substrate holder comprising: a first holding member; and a second holding member configured to hold the substrate between the first holding member and the second holding member, wherein the first holding member comprises: at least one substrate contact arranged to come into contact with the substrate; at least one seal member provided with a first seal portion configured to cover periphery of a leading end portion of one or a plurality of the substrate contacts; and at least one bus bar electrically connected with the one or plurality of substrate contacts and provided with one or a plurality of first through holes to receive the first seal portion, wherein the leading end portion of the one or plurality of substrate contacts is arranged to pass through the first through hole from a side opposite to the second holding member toward the second holding member and is fixed to the bus bar in a state that the periphery of the leading end portion of the one or plurality of substrate contacts is covered by the first seal portion.

An interconnect structure of a semiconductor device includes a conductive via and a barrier layer lining an interface between a dielectric layer and the conductive via. The barrier layer is selectively deposited along sidewalls of a recess formed in a dielectric layer. The conductive via is formed by selectively electroplating electrically conductive material such as rhodium, iridium, or platinum in an opening of the recess, where the conductive via is grown upwards from an exposed metal surface at a bottom of the recess. The conductive via includes an electrically conductive material having a low electron mean free path, low electrical resistivity, and high melting point. The interconnect structure of the semiconductor device has reduced via resistance and improved resistance to electromigration and/or stress migration.

A method of plating a metal layer on a work piece includes exposing a surface of the work piece to a plating solution, and supplying a first voltage at a negative end of a power supply source to an edge portion of the work piece. A second voltage is supplied to an inner portion of the work piece, wherein the inner portion is closer to a center of the work piece than the edge portion. A positive end of the power supply source is connected to a metal plate, wherein the metal plate and the work piece are spaced apart from each other by, and are in contact with, the plating solution.

There is provided the substrate holder for holding a substrate comprising a first holding member, a second holding member, a sealing member, a pin, a ring, and a moving mechanism. The sealing member forms a sealed space inside the substrate holder. The pin is fixed to one of the first holding member and the second holding member. The ring is disposed on another of the first holding member and the second holding member. The ring engages with the pin. The moving mechanism circumferentially moves the ring. The pin and the ring are engaged with one another to fix the first holding member and the second holding member to one another. The pin and the ring are disposed inside the sealed space.

Undesired deposition of metals on a lipseal (lipseal plate-out) during electrodeposition of metals on semiconductor substrates is minimized or eliminated by minimizing or eliminating ionic current directed at a lipseal. For example, electrodeposition can be conducted such as to avoid contact of a lipseal with a cathodically biased conductive material on the semiconductor substrate during the course of electroplating. This can be accomplished by shielding a small selected zone proximate the lipseal to suppress electrode-position of metal proximate the lipseal, and to avoid contact of metal with a lipseal. In some embodiments shielding is accomplished by sequentially using lipseals of different inner diameters during electroplating of metals into through-resist features, where a lipseal having a smaller diameter is used during a first electroplating step and serves as a shield blocking electrodeposition in a selected zone. In a second electroplating step, a lipseal of a larger inner diameter is used.

Provided is a plating apparatus and a plating solution agitating method that can agitate a plating solution without using a paddle.

A plating apparatus 1000 includes a holder cover 50 disposed in a substrate holder 30 and configured to rotate with the substrate holder when the substrate holder rotates. The holder cover is configured to have a lower surface immersed in the plating solution with the lower surface positioned below a surface to be plated of a substrate. The lower surface of the holder cover is provided with at least one cover groove extending in a direction intersecting with a rotation direction of the holder cover.