A gas phase nanowire growth apparatus including a reaction chamber, a first input and a second input. The first input is located concentrically within the second input and the first and second input are configured such that a second input fluid delivered from the second input provides a sheath between a first fluid delivered from the first input and a wall of the reaction chamber. An aerosol of catalyst particles may be used to grow the nanowires.

Methods and wafers for low etch pit density, low slip line density, and low strain indium phosphide are disclosed and may include an indium phosphide single crystal wafer having a diameter of 4 inches or greater, having a measured etch pit density of less than 500 cm.sup.?2, and having fewer than 5 dislocations or slip lines as measured by x-ray diffraction imaging. The wafer may have a measured etch pit density of 200 cm.sup.?2 or less, or 100 cm.sup.?2 or less, or 10 cm.sup.?2 or less. The wafer may have a diameter of 6 inches or greater. An area of the wafer with a measured etch pit density of zero may at least 80% of the total area of the surface. An area of the wafer with a measured etch pit density of zero may be at least 90% of the total area of the surface.

Disclosed is a method for melting and solidification of a scintillating material in micromechanical structures, including controlling the melting and solidification of the scintillating material by individually controlled heat sources, a top heater and a bottom heater, placed above and below a process chamber, housing a sample with the micromechanical structures and the scintillating material. The heaters are controlled to set a vertical temperature gradient over the sample to control the melting and solidification of the scintillating material. During melting, the top heater is ramped up and stabilized at a temperature where no melting occurs and the bottom heater is ramped up and stabilized at a temperature where melting occurs during a period of time while the scintillating material melts and flows into the micromechanical structures. During solidification, the temperature of the bottom heater decreases to enable solidification to take place starting from the bottom of the micromechanical structures.

A crystalline silicon ingot and a method of fabricating the same are disclosed. The crystalline silicon ingot of the invention includes multiple silicon crystal grains growing in a vertical direction of the crystalline silicon ingot. The crystalline silicon ingot has a bottom with a silicon crystal grain having a first average crystal grain size of less than about 12 mm. The crystalline silicon ingot has an upper portion, which is about 250 mm away from said bottom, with a silicon crystal grain having a second average crystal grain size of greater than about 14 mm.

The present invention relates to a scintillator, a method for manufacturing the same, and an application for the same. The scintillator according to an embodiment of the present invention includes a matrix material including, as a main component, thallium, lanthanum, and a halogen element; and an activator doped onto the matrix material. The scintillator according to an embodiment of the present invention has a formula TlaLabXc:yCe, and in the formula: X is a halogen element; a=1, b=2, c=7, or a=2, b=1, c=5, or a=3, b=1, c=6; and y>0 and y0.5. The scintillator according to an embodiment of the present invention has a high efficiency of detecting radiations, a greater light yield, and an excellent fluorescence decay time characteristic.

Embodiments of the present invention relate to a furnace system for growing crystals. The furnace system comprises a crucible for growing a crystal and a furnace comprising a housing having an inner volume. The housing comprises a through hole connecting the inner volume with an environment of the housing. An insulation plug is movably insertable into the through hole for controlling a heat extraction out of the crucible by radiation, wherein the insulation plug is free of a force transmitting contact with the crucible.

A system comprises a silicon seed arranged on a pedestal, where the silicon seed is ring shaped and is configured to receive melted silicon at a feed rate to form an ingot, and where the pedestal is configured to rotate at a rotational speed. A controller is configured to, while the silicon seed receives the melted silicon and while the ingot is forming: receive feedback regarding a diameter of the ingot and regarding an angle of a meniscus of the ingot, and control the rotational speed of the pedestal and the feed rate of the melted silicon based on the feedback to control the diameter of the ingot and the angle of the meniscus of the ingot

The present disclosure relates to the field of directional solidification, and in particular, to an apparatus, method, and process for directional solidification by liquid metal spraying enhanced cooling (LMSC). The process has the following beneficial effects: the apparatus of the present disclosure can regulate a solidification structure of a casting, refine a dendrite spacing, and reduce or avoid metallurgical defects, and can be used to prepare high-quality large-sized columnar/single crystal blades or other castings.

Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm.sup.?2, and a resistivity of 1?10.sup.7 ?-cm or more. The wafer may have an optical absorption of less than 5 cm.sup.?1 less than 4 cm.sup.?1 or less than 3 cm.sup.?1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm.sup.2/V-sec or higher. The wafer may have a thickness of 500 ?m or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1?10.sup.7 cm.sup.?3 or less.

A method for manufacturing a silicon ingot having uniform phosphorus concentration. The method includes at least the steps of: (i) providing a quasi-uniform molten silicon bath containing at least phosphorus; and (ii) proceeding to the directional solidification of the silicon, wherein a speed (VI) for solidifying the silicon and a rate (JLV) of evaporation of the phosphorus at the liquid/vapor interface of the bath are controlled such that, at each moment of the directional solidification, the following equation is verified: VI=k/(2k) (E), wherein k is the phosphorus transfer coefficient, and k is the distribution coefficient of the phosphorus in the silicon. Also relates to a silicon ingot having uniform phosphorus concentration across a height of at least 20 cm.