C30B15/20

Indium phosphide wafer, photoelectric conversion element, and method for producing a monocrystalline indium phosphide

In this photoelectric conversion element wherein group III-IV compound semiconductor single crystals containing zinc as an impurity are used as a substrate, the substrate is increased in size without lowering conversion efficiency. A heat-resistant crucible is filled with raw material and a sealant, and the raw material and sealant are heated, thereby melting the raw material into a melt, softening the encapsulant, and covering the melt from the top with the encapsulant. The temperature inside the crucible is controlled such that the temperature of the top of the encapsulant relative to the bottom of the encapsulant becomes higher in a range that not equal or exceed the temperature of bottom of the encapsulant, and seed crystal is dipped in the melt and pulled upward with respect to the melt, thereby growing single crystals from the seed crystal. Thus, a large compound semiconductor wafer that is at least two inches in diameter and has a low dislocation density of 5,000 cm.sup.−2 can be obtained, despite having a low average zinc concentration of 5×10.sup.17 cm.sup.−3 to 3×10.sup.18 cm.sup.−3, at which a crystal hardening effect does not manifest.

Indium phosphide wafer, photoelectric conversion element, and method for producing a monocrystalline indium phosphide

In this photoelectric conversion element wherein group III-IV compound semiconductor single crystals containing zinc as an impurity are used as a substrate, the substrate is increased in size without lowering conversion efficiency. A heat-resistant crucible is filled with raw material and a sealant, and the raw material and sealant are heated, thereby melting the raw material into a melt, softening the encapsulant, and covering the melt from the top with the encapsulant. The temperature inside the crucible is controlled such that the temperature of the top of the encapsulant relative to the bottom of the encapsulant becomes higher in a range that not equal or exceed the temperature of bottom of the encapsulant, and seed crystal is dipped in the melt and pulled upward with respect to the melt, thereby growing single crystals from the seed crystal. Thus, a large compound semiconductor wafer that is at least two inches in diameter and has a low dislocation density of 5,000 cm.sup.−2 can be obtained, despite having a low average zinc concentration of 5×10.sup.17 cm.sup.−3 to 3×10.sup.18 cm.sup.−3, at which a crystal hardening effect does not manifest.

INGOT PULLER APPARATUS HAVING SILICON FEED TUBES WITH KICK PLATES

Ingot puller apparatus that include a silicon feed tube for adding solid silicon to a crucible assembly are disclosed. The silicon feed tubes include a conduit portion having an inner diameter and a kick plate disposed below the conduit portion. The kick plate extends across at least 60% of the inner diameter of the conduit portion.

INGOT PULLER APPARATUS HAVING SILICON FEED TUBES WITH KICK PLATES

Ingot puller apparatus that include a silicon feed tube for adding solid silicon to a crucible assembly are disclosed. The silicon feed tubes include a conduit portion having an inner diameter and a kick plate disposed below the conduit portion. The kick plate extends across at least 60% of the inner diameter of the conduit portion.

Resistivity stabilization measurement of fat neck slabs for high resistivity and ultra-high resistivity single crystal silicon ingot growth

Methods for forming single crystal silicon ingots with improved resistivity control are disclosed. The methods involve growth of a sample rod. The sample rod may have a diameter less than the diameter of the product ingot. The sample rod is cropped to form a center slab. The resistivity of the center slab may be measured directly such as by a four-point probe. The sample rod or optionally the center slab may be annealed in a thermal donor kill cycle prior to measuring the resistivity, and the annealed rod or slab is irradiated with light in order to enhance the relaxation rate and enable more rapid resistivity measurement.

NON-CONTACT SYSTEMS AND METHODS FOR DETERMINING DISTANCE BETWEEN SILICON MELT AND REFLECTOR IN A CRYSTAL PULLER
20220154365 · 2022-05-19 ·

A measurement system includes a reflector defining a central passage and an opening, a measurement assembly, and a controller. The measurement assembly includes a run pin having a head that is visible through the opening, a camera to capture images through the opening in the reflector, and a laser to transmit coherent light through the opening to the head of the run pin to produce a reflection of the run pin on the surface of the silicon melt. The controller is programmed to control the laser to direct coherent light from the laser to the run pin, control the camera capture images through the opening while the coherent light is directed at the run pin, and determine a distance between the surface of the silicon melt and a bottom surface of the reflector based on a location of the reflection of the run pin in the captured images.

NON-CONTACT SYSTEMS AND METHODS FOR DETERMINING DISTANCE BETWEEN SILICON MELT AND REFLECTOR IN A CRYSTAL PULLER
20220154365 · 2022-05-19 ·

A measurement system includes a reflector defining a central passage and an opening, a measurement assembly, and a controller. The measurement assembly includes a run pin having a head that is visible through the opening, a camera to capture images through the opening in the reflector, and a laser to transmit coherent light through the opening to the head of the run pin to produce a reflection of the run pin on the surface of the silicon melt. The controller is programmed to control the laser to direct coherent light from the laser to the run pin, control the camera capture images through the opening while the coherent light is directed at the run pin, and determine a distance between the surface of the silicon melt and a bottom surface of the reflector based on a location of the reflection of the run pin in the captured images.

METHODS FOR FORMING A SILICON SUBSTRATE WITH REDUCED GROWN-IN NUCLEI FOR EPITAXIAL DEFECTS AND METHODS FOR FORMING AN EPITAXIAL WAFER
20220145493 · 2022-05-12 ·

Methods for preparing single crystal silicon substrates for epitaxial growth are disclosed. The methods may involve control of the (i) a growth velocity, v, and/or (ii) an axial temperature gradient, G, during the growth of an ingot segment such that v/G is less than a critical v/G and/or is less than a value of v/G that depends on the boron concentration of the ingot. Methods for preparing epitaxial wafers are also disclosed.

METHODS FOR PREPARING AN INGOT IN AN INGOT PULLER APPARATUS AND METHODS FOR SELECTING A SIDE HEATER LENGTH FOR SUCH APPARATUS
20220145490 · 2022-05-12 ·

Methods for preparing an ingot in an ingot puller apparatus are disclosed. Thermal simulations are performed with the length of the ingot puller apparatus side heater being varied in the thermal simulations. A side heater is selected based on the thermal simulations. An ingot puller apparatus having the selected side heater length is provided. A seed crystal is lowered into a melt within a crucible of the ingot puller apparatus and an ingot is withdrawn from the melt.

METHODS FOR PREPARING AN INGOT IN AN INGOT PULLER APPARATUS AND METHODS FOR SELECTING A SIDE HEATER LENGTH FOR SUCH APPARATUS
20220145490 · 2022-05-12 ·

Methods for preparing an ingot in an ingot puller apparatus are disclosed. Thermal simulations are performed with the length of the ingot puller apparatus side heater being varied in the thermal simulations. A side heater is selected based on the thermal simulations. An ingot puller apparatus having the selected side heater length is provided. A seed crystal is lowered into a melt within a crucible of the ingot puller apparatus and an ingot is withdrawn from the melt.