A method for preparing suspended graphene support film by selectively etching growth substrate is disclosed in present invention. The transfer process of graphene is avoided. The process of present invention is efficient and low in cost, suspended graphene support film can be prepared in a single etching step. The prepared graphene support film does not need any support by polymer film and polymer fiber. The prepared graphene support film has controllable number of layers and high intactness (90%-97%), large suspended area (diameter is 10-50 μm), wide clean area (>100 nm) and can be mass-produced. In addition, the graphene support film can be directly used as transmission electron microscope support film, and can be used to achieve high resolution imaging of nanoparticles.

A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.

A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.

A large grain quasi-single-crystal film and a manufacturing method thereof are provided. The metal film having the <111> preferred orientation on its surface is subjected to mechanical tensile force to make the arrangement of crystal grains more ordered. The metal film is grown into a film with large crystal grains having an average diameter of over 500 microns by annealing at a temperature below the recrystallization temperature, thereby obtaining a large grain quasi-single-crystal film having the preferred directions of three axes. The large grain quasi-single-crystal film has a <110> preferred orientation along the tensile direction and a <211> preferred orientation along the direction vertical to the tensile force, and maintains a <111> preferred orientation on its top surface. The present invention can be used to produce highly anisotropic large-area quasi-single-crystal films, and can also be applied to grow 2-dimensional materials or develop anisotropic structures.

The present invention relates to novel gold nanocrystals and nanocrystal shape distributions that have surfaces that are substantially free from organic impurities or films. Specifically, the surfaces are “clean” relative to the surfaces of gold nanoparticles made using chemical reduction processes that require organic reductants and/or surfactants to grow gold nanoparticles from gold ions in solution.

The invention includes novel electrochemical manufacturing apparatuses and techniques for making the gold-based nanocrystals. The invention further includes pharmaceutical compositions thereof and the use of the gold nanocrystals or suspensions or colloids thereof for the treatment or prevention of diseases or conditions for which gold therapy is already known and more generally for conditions resulting from pathological cellular activation, such as inflammatory (including chronic inflammatory) conditions, autoimmune conditions, hypersensitivity reactions and/or cancerous diseases or conditions. In one embodiment, the condition is mediated by MT (macrophage migration inhibiting factor).

The present invention relates to novel gold nanocrystals and nanocrystal shape distributions that have surfaces that are substantially free from organic impurities or films. Specifically, the surfaces are “clean” relative to the surfaces of gold nanoparticles made using chemical reduction processes that require organic reductants and/or surfactants to grow gold nanoparticles from gold ions in solution.

The invention includes novel electrochemical manufacturing apparatuses and techniques for making the gold-based nanocrystals. The invention further includes pharmaceutical compositions thereof and the use of the gold nanocrystals or suspensions or colloids thereof for the treatment or prevention of diseases or conditions for which gold therapy is already known and more generally for conditions resulting from pathological cellular activation, such as inflammatory (including chronic inflammatory) conditions, autoimmune conditions, hypersensitivity reactions and/or cancerous diseases or conditions. In one embodiment, the condition is mediated by MT (macrophage migration inhibiting factor).

Core-shell nanostructures with platinum overlayers conformally coating palladium nano-substrate cores and facile solution-based methods for the preparation of such core-shell nanostructures are described herein. The obtained Pd@Pt core-shell nanocatalysts showed enhanced specific and mass activities towards oxygen reduction, compared to a commercial Pt/C catalyst.

Core-shell nanostructures with platinum overlayers conformally coating palladium nano-substrate cores and facile solution-based methods for the preparation of such core-shell nanostructures are described herein. The obtained Pd@Pt core-shell nanocatalysts showed enhanced specific and mass activities towards oxygen reduction, compared to a commercial Pt/C catalyst.

A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.

A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.