C30B33/08

EPITAXIAL SILICON CHANNEL GROWTH

A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.

Group-III nitride substrate

A group-III nitride substrate includes: a first region having a first impurity concentration in a polished surface; and a second region having a second impurity concentration lower than the first impurity concentration in the polished surface, wherein a first dislocation density of the first region is lower than a second dislocation density of the second region.

Group-III nitride substrate

A group-III nitride substrate includes: a first region having a first impurity concentration in a polished surface; and a second region having a second impurity concentration lower than the first impurity concentration in the polished surface, wherein a first dislocation density of the first region is lower than a second dislocation density of the second region.

ENGINEERED SUBSTRATE STRUCTURES FOR POWER AND RF APPLICATIONS
20220301855 · 2022-09-22 · ·

A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial III-V layers by epitaxial growth on the epitaxial silicon layer.

ENGINEERED SUBSTRATE STRUCTURES FOR POWER AND RF APPLICATIONS
20220301855 · 2022-09-22 · ·

A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial III-V layers by epitaxial growth on the epitaxial silicon layer.

NON-CONTACT POLISHING OF A CRYSTALLINE LAYER OR SUBSTRATE BY ION BEAM ETCHING
20220275533 · 2022-09-01 ·

Polishing method comprising the steps of: —providing at least one crystalline layer or substrate, the at least one crystalline layer or substrate extending in at least one plane, and including at least one outer surface and at least one depression extending from the at least one outer surface; and —polishing the at least one outer surface using ion beam etching (IBE) or an accelerated inert gas ion beam, the ion beam being incident on the at least one outer surface at non-normal incidence or at a non-zero angle (θ) with respect to the surface normal of the at least one plane of the crystalline layer or substrate.

Group 13 Element Nitride Wafer With Reduced Variation In Off-Cut Angle

The invention relates to a two-dimensional crystal wafer of group 13 or III element nitride which is delimited by a face of orientation N, an opposing face of orientation E depending on the group 13 or III element, E being selected preferably from Ga, In, Al or a combination of these elements, charaterized in that the variation in crstalline off-cut angle in the largest dimension of said wafer is less than 5×10−3°/mm, and its curvature of geometric deformation of its faces exhibits a flexure in terms of absolute value of less than 10−.sup.3mm/mm of the largest dimension of said wafer.

Group 13 Element Nitride Wafer With Reduced Variation In Off-Cut Angle

The invention relates to a two-dimensional crystal wafer of group 13 or III element nitride which is delimited by a face of orientation N, an opposing face of orientation E depending on the group 13 or III element, E being selected preferably from Ga, In, Al or a combination of these elements, charaterized in that the variation in crstalline off-cut angle in the largest dimension of said wafer is less than 5×10−3°/mm, and its curvature of geometric deformation of its faces exhibits a flexure in terms of absolute value of less than 10−.sup.3mm/mm of the largest dimension of said wafer.

Methods of manufacturing engineered substrate structures for power and RF applications

A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial layers by epitaxial growth on the epitaxial silicon layer.

Methods of manufacturing engineered substrate structures for power and RF applications

A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial layers by epitaxial growth on the epitaxial silicon layer.