Exemplary methods of forming a semiconductor structure may include forming a nucleation layer on a semiconductor substrate. The exemplary methods may further include forming at least one gallium nitride (GaN)-containing region on the nucleation layer, and forming an indium-gallium-nitride (InGaN)-containing layer on the GaN-containing region. A porosified region may be formed on a portion of at least one of the GaN-containing region and the InGaN-containing layer, and an active region may be formed on the porosified region. In embodiments, the porosified region may be characterized by a void fraction of greater than or about 20 vol. %. In further embodiments, the active region may include a greater mole percentage (mol. %) indium than the porosified region or the GaN-containing region. In still further embodiments, the active region may characterized by a peak light emission at a wavelength of greater than or about 620 nm.

Exemplary methods of forming a semiconductor structure may include forming a nucleation layer on a semiconductor substrate. The exemplary methods may further include forming at least one gallium nitride (GaN)-containing region on the nucleation layer, and forming an indium-gallium-nitride (InGaN)-containing layer on the GaN-containing region. A porosified region may be formed on a portion of at least one of the GaN-containing region and the InGaN-containing layer, and an active region may be formed on the porosified region. In embodiments, the porosified region may be characterized by a void fraction of greater than or about 20 vol. %. In further embodiments, the active region may include a greater mole percentage (mol. %) indium than the porosified region or the GaN-containing region. In still further embodiments, the active region may characterized by a peak light emission at a wavelength of greater than or about 620 nm.

Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

An apparatus for producing an SiC substrate, by which an SiC substrate having a thin base substrate layer is able to be produced, while suppressing deformation or breakage, includes a main container which is capable of containing an SiC base substrate, and which produces a vapor pressure of a vapor-phase species containing elemental Si and a vapor-phase species containing elemental C within the internal space by means of heating; and a heating furnace which contains the main container and heats the main container so as to form a temperature gradient, while producing a vapor pressure of a vapor-phase species containing elemental Si within the internal space. The main container has a growth space in which a growth layer is formed on one surface of the SiC base substrate, and an etching space in which the other surface of the SiC base substrate is etched.

An apparatus for producing an SiC substrate, by which an SiC substrate having a thin base substrate layer is able to be produced, while suppressing deformation or breakage, includes a main container which is capable of containing an SiC base substrate, and which produces a vapor pressure of a vapor-phase species containing elemental Si and a vapor-phase species containing elemental C within the internal space by means of heating; and a heating furnace which contains the main container and heats the main container so as to form a temperature gradient, while producing a vapor pressure of a vapor-phase species containing elemental Si within the internal space. The main container has a growth space in which a growth layer is formed on one surface of the SiC base substrate, and an etching space in which the other surface of the SiC base substrate is etched.

A process of preparing a wafer having a diameter of two inches or more, at least a surface of the wafer being formed from a group III nitride crystal, including preparing an alkaline or acidic etching liquid containing a peroxodisulfate ion as an oxidizing agent that accepts an electron, accommodating the wafer such that the surface of the wafer is immersed in the etching liquid such that the surface of the wafer is parallel with a surface of the etching liquid; and radiating light from the surface side of the etching liquid onto the surface of the wafer without agitating the etching liquid. First and second etching areas disposed at an interval from each other are defined on the surface of the wafer. In the process of radiating the light onto the surface of the wafer, the light is radiated perpendicularly onto surfaces of the first and second etching areas.

The present invention provides a method for analyzing a silicon substrate, by which impurities such as a very small amount of metal in a silicon substrate provided with a thick nitride film can be analyzed with high accuracy with ICP-MS, and is characterized by use of a silicon substrate analysis apparatus including an analysis scan port having a load port, a substrate conveyance robot, an aligner, a drying chamber, a vapor phase decomposition chamber, an analysis stage and a nozzle for analysis of a substrate; an analysis liquid collection unit; and an analyzer for performing inductive coupling plasma analysis.

The present invention provides a method for analyzing a silicon substrate, by which impurities such as a very small amount of metal in a silicon substrate provided with a thick nitride film can be analyzed with high accuracy with ICP-MS, and is characterized by use of a silicon substrate analysis apparatus including an analysis scan port having a load port, a substrate conveyance robot, an aligner, a drying chamber, a vapor phase decomposition chamber, an analysis stage and a nozzle for analysis of a substrate; an analysis liquid collection unit; and an analyzer for performing inductive coupling plasma analysis.

An 8-inch SiC single crystal substrate of an embodiment has a diameter in a range of 195 mm to 205 mm, a thickness in a range of 300 μm to 650 μm, a SORT of 50 μm or less, and an in-plane variation of the thickness of the substrate, which is the difference between the maximum and minimum substrate thickness at the center of the substrate and four points on the circumference of a circle having a radius half the radius of the substrate, is 1.5 μm or less.

An 8-inch SiC single crystal substrate of an embodiment has a diameter in a range of 195 mm to 205 mm, a thickness in a range of 300 μm to 650 μm, a SORT of 50 μm or less, and an in-plane variation of the thickness of the substrate, which is the difference between the maximum and minimum substrate thickness at the center of the substrate and four points on the circumference of a circle having a radius half the radius of the substrate, is 1.5 μm or less.