An intercalation doping apparatus including: a reactor chamber where single or multiple wafers or substrates (SoMWoSubs) are disposed within the reactor chamber, where SOMWoSubs have a diameter or a side distance from 25 mm to 450 mm; a heater, where the heater is configured to provide heat to the SOMWoSubs disposed within the reactor chamber, where the SoMWoSubs include a temperature from 25 C. to 500 C.; where pressure is applied to at least one surface of the SOMWoSubs disposed within the reactor chamber within a range of 2 bar to 500 bar; and a dopant application apparatus, where the dopant application apparatus includes at least valves and tubing which bring dopants from outside to within the reactor chamber and includes at least a dopant crucible disposed within the reactor chamber, where the dopants include material in solid, liquid, or gaseous phase, and where the dopants include intercalation doping agents.

A process for forming a device can include forming a first semiconductor region having a first conductivity type. The process can include depositing a dielectric layer over the first semiconductor region, the dielectric layer having a first etch rate. The process can include forming a first photoresist layer having a second etch rate that is greater than the first etch rate over the dielectric layer and forming a second photoresist layer over the first photoresist layer. The process can include patterning the second photoresist layer to remove a region of the second photoresist, the first photoresist layer being exposed under the region. The process can include etching to form a beveled structure in the dielectric layer. The process can include removing the first photoresist layer and the second photoresist layer and performing ion implantation of the first semiconductor region with dopant species having a second conductivity type.

A conformal boron doping method for a three-dimensional structure includes the steps of: removing a natural oxide layer on a surface of a silicon-based three-dimensional substrate; forming a buffer layer on the surface of the silicon-based three-dimensional substrate; forming a boron oxide thin film on the alumina buffer layer; covering a passivation layer on a surface of the boron oxide thin film; and driving boron impurities containing boron oxide into the silicon-based three-dimensional substrate through the buffer layer by using laser or rapid annealing, to dope the silicon-based three-dimensional substrate. Selecting suitable boron source precursors and oxidants solves the problems of difficult nucleation and inability to form a film after reaching a certain thickness for boron oxide. By selecting alumina as the passivation layer, it is possible to protect the boron oxide thin film from being damaged, and thus achieve damage-free diffusion doping during laser or rapid annealing processes.

In at least one embodiment, the method is for producing a semiconductor device (1) and comprises the following steps in the stated order: A) providing a semiconductor body (2) having a top side (20), the semiconductor body (2) is based on SiC, B) producing a first layer (21) of the semiconductor body (2) next to the top side (20) by doping with a dopant (4), C) applying a carbon-containing layer (3) on the top side (20), D) implanting C into the first layer (21) through the carbon-containing layer (3), and E) performing a temperature treatment of the semiconductor body (2) when the carbon-containing layer (3) is still present on the top side (20).

The present disclosure provides a DMOS device with a junction field plate and its manufacturing method. A drain region is located on a surface of a semiconductor substrate. A source region is located in the semiconductor substrate at a bottom of a first trench. A gate electrode is located at the bottom of the first trench. The junction field plate improves an effect on reducing surface resistance. At the same time, a depth of trenches in the DMOS device may be reduced, and thereby a depth-to-width ratio of the device is reduced, improving the feasibility of increasing a voltage resistance level. Both the source region and the drain region in the DMOS device are led out on a same surface. A second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer with different conduction types.