A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a base structure, a bit line structure and a spacer. The bit line structure is disposed over the base structure. The spacer is disposed around the bit line structure, and includes a first layer, a second layer and a third layer. The third layer is disposed over the second layer. A width of the third layer is substantially equal to a width of the second layer.

A semiconductor structure and a preparation method therefor, a functional chip, and an electronic device. The method includes providing a semiconductor layer group, which includes a first dielectric layer, a semiconductor layer, a conductive structure, and an electronic element. A part of the semiconductor layer is removed from a side of a second surface of the semiconductor layer along a first direction, to expose an end face of the conductive structure away from the electronic element. A protection structure is formed on a side of the conductive structure away from the first dielectric layer, where an orthographic projection of the protection structure on the semiconductor layer covers an orthographic projection of the exposed end face of the conductive structure on the semiconductor layer. The part of the semiconductor layer is etched from the side of the second surface of the semiconductor layer along the first direction using the protection structure as a mask.

Dual-damascene fully-aligned via interconnects with divot fill are provided. In one aspect, an interconnect structure includes: a first interlayer dielectric disposed on a wafer; a metal line(s) embedded in the first interlayer dielectric, where a top surface of the metal line(s) is recessed below a top surface of the first interlayer dielectric; a second interlayer dielectric disposed on the first interlayer dielectric; a conductive via(s) embedded in the second interlayer dielectric and aligned with the metal line(s); a barrier layer along a bottom and a first portion of a sidewall of the metal line(s); and a protective dielectric layer along a second portion of the sidewall of the metal line(s), where the barrier layer and the protective dielectric layer fully separate the metal line(s) from the first interlayer dielectric. A metal cap can be disposed on the metal line(s). A method of fabricating an interconnect structure is also provided.