Patent classifications
H10W72/01331
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
A semiconductor package includes a substrate, a device die, an encapsulating material, a thermal conductive layer, a filling material, and a carrier. The device die is disposed over the substrate. The encapsulating material is disposed over the substrate and laterally encapsulates the device die. The thermal conductive layer conformally covers the device die and the encapsulating material, wherein a profile of the thermal conductive layer comprises a valley portion. The filling material is disposed over the thermal conductive layer and fills the valley portion, wherein a thermal conductivity of the thermal conductive layer is higher than a thermal conductivity of the filling material. The carrier is bonded to the thermal conductive layer and the filling material.
Packaged microelectronic devices having stacked interconnect elements and methods for manufacturing the same
Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.