Aspects disclosed in the detailed description include an integrated circuit (IC) package employing a metal block with metal interconnects thermally coupling a semiconductor die (die) to an interposer substrate for dissipating thermal energy in the die. The die is coupled to a package substrate to provide signal routing paths to the die. To facilitate additional dies being stacked in the IC package as a three-dimensional (3D) IC (3DIC) package, the IC package also includes an interposer substrate adjacent to the die. The interposer substrate supports providing additional signal routing paths to the package substrate. The interposer substrate also includes a metal block which comprises a plurality of metal layers and is thermally coupled to the die and a metal interconnect(s) in the interposer substrate to dissipate thermal energy from the die through the metal block and through the coupled metal interconnect(s).

An apparatus including a substrate having a first surface, and a silicon interposer including a first surface and a second surface, wherein the first surface is connected to the first surface of the substrate. The apparatus also includes at least one stack including an artificial intelligence (AI) chiplet and a plurality of static random-access memories (SRAMs) stacked below the AI chiplet, wherein the at least one stack includes a top surface, a bottom surface, a first side surface and a second side surface, and the at least one stack is orthogonally attached by the first side surface to the second surface of the silicon interposer. The apparatus additionally includes a heat spreader surrounding the top surface, the bottom surface and the second side surface of the at least one stack.

A semiconductor structure and semiconductor device are provided. The semiconductor structure includes a plurality of layers of memory modules stacked on an upper surface of the logic chip in a first direction which is perpendicular to the upper surface of the logic chip. Each storage module includes a plurality of memory chips stacked in a second direction which is parallel to the upper surface. Each memory chip in a top layer includes one second wireless communication part; and each memory chip in a non-top layer includes two second wireless communication parts arranged in the first direction and a wired communication part connected between the two second wireless communication parts. Two adjacent second wireless communication parts located on different memory chips in the first direction communicate with each other wirelessly; and each first wireless communication part communicates wirelessly with a closest second wireless communication part in a bottom memory chip.